M3087BFKBGP#U3 Renesas Electronics America, M3087BFKBGP#U3 Datasheet - Page 450
M3087BFKBGP#U3
Manufacturer Part Number
M3087BFKBGP#U3
Description
IC M32C/87B MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFKBGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M3087BFKBGP#U3M3087BFKBGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 426 of 587
Figure 23.19
23.1.16 CANi Mode Register (CiMDR Register) (i = 0, 1)
23.1.16.1 CMOD Bit
CANi Mode Register (i = 0, 1)
b7 b6 b5 b4
The CMOD bit selects a CAN operating mode.
NOTE:
NOTES:
•
•
•
1. Do not generate a transmit request in bus monitoring mode.
1. Set the CiMDR register while the STATE_RESET bit in the CiSTR register is 1 (CAN module is in reset).
2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the
Normal operating mode: Normal transmit and receive operations are enabled.
Bus monitoring mode
to high level (“H”) in bus monitoring mode. The CAN module transmits neither ACK nor error frame.
Self-test mode: The CAN module connects the CANiOUT pin to the CANiIN pin internally. The CAN
module can communicate without additional device when using self-test mode and loop back mode. Output
signal from the CANiOUT pin is fixed to “H” in self-test mode while transmitting. Figure 23.20 shows an
image diagram in self-test mode.
clock to the CAN module.
The CAN module in bus monitoring mode considers dominant “L” is received regardless of whether the
actual ACK bit is dominant “L” or recessive “H”. Therefore, when a transmit operation is completed until
EOF, the CAN module determines a receive operation is successfully completed even if the ACK bit is
recessive “H”.
b3
b2
C0MDR and C1MDR Registers
b1
b0
Bit Symbol
(b7-b2)
CMOD
Symbol
C0MDR
C1MDR
−
(1)
: Only receive operation is enabled. Output signal from the CANiOUT pin is fixed
CAN operating mode
select bit
Unimplemented.
Write 0. Read as undefined value.
(1)
Bit Name
Address
0219h
0299h
b1 b0
0 0: Normal operating mode
0 1: Bus monitoring mode
1 0: Self-test mode
1 1: Do not set to this value
Function
After Reset
XXXX XX00b
XXXX XX00b
23. CAN Module
(2)
RW
RW
RW
−
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