PIC16F688-I/STG Microchip Technology, PIC16F688-I/STG Datasheet - Page 113

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PIC16F688-I/STG

Manufacturer Part Number
PIC16F688-I/STG
Description
IC PIC MCU FLASH 4KX14 14TSSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F688-I/STG

Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-TSSOP
For Use With
XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
REGISTER 11-1:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
Reserved
CPD
2:
3:
4:
(2)
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire data EEPROM will be erased when the code protection is turned off.
The entire program memory will be erased when the code protection is turned off.
When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
Reserved: Reserved bits. Do Not Use.
FCMEN: Fail-Safe Clock Monitor Enabled bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switchover mode is disabled
BOREN<1:0>: Brown-out Reset Selection bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the PCON register
00 = BOR disabled
CPD: Data Code Protection bit
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
MCLRE: MCLR Pin Function Select bit
1 = MCLR pin function is MCLR
0 = MCLR pin function is digital input, MCLR internally tied to V
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
FOSC<2:0>: Oscillator Selection bits
111 = EXTRC oscillator: External RC on RA5/OSC1/CLKIN, CLKOUT function on RA4/OSC2/CLKOUT pin
110 = EXTRCIO oscillator: External RC on RA5/OSC1/CLKIN, I/O function on RA4/OSC2/CLKOUT pin
101 = INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on
100 = INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on
011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
Reserved
CP
CONFIG: CONFIGURATION WORD REGISTER
RA5/OSC1/CLKIN
RA5/OSC1/CLKIN
(3)
W = Writable bit
‘1’ = Bit is set
MCLRE
Reserved
(2)
(4)
(2)
Reserved
PWRTE
(3)
(1)
P = Programmable’
‘0’ = Bit is cleared
FCMEN
WDTE
DD
FOSC2
IESO
U = Unimplemented bit, read
as ‘0’
x = Bit is unknown
PIC16F688
BOREN1
FOSC1
DS41203E-page 111
(1)
BOREN0
FOSC0
bit 8
bit 0
(1)

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