PIC16F688-I/STG Microchip Technology, PIC16F688-I/STG Datasheet - Page 49

• Manufacturer Part Number: PIC16F688-I/STG
• Description: IC PIC MCU FLASH 4KX14 14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/STG

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• For Use With: XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 5-1:
TABLE 5-1:
© 2009 Microchip Technology Inc.
TMR0
INTCON
OPTION_REG
TRISA
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
R/W-1
RAPU
Name
Timer0 module.
A dedicated 16-bit WDT postscaler is available. See Section 11.5 “Watchdog Timer (WDT)” for more
information.
RAPU: PORTA Pull-up Enable bit
1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (F
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Timer0 Module Register
RAPU INTEDG
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7
INTEDG
GIE
R/W-1
—
OPTION_REG: OPTION REGISTER
BIT VALUE
PEIE
Bit 6
000
001
010
011
100
101
110
111
—
W = Writable bit
‘1’ = Bit is set
R/W-1
T0CS
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
T0CS
Bit 5
TMR0 RATE
T0IE
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
T0SE
Bit 4
INTE
R/W-1
T0SE
WDT RATE
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
OSC
RAIE
Bit 3
PSA
/4)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
PSA
Bit 2
T0IF
PS2
INTF
Bit 1
PS1
R/W-1
PS2
RAIF
Bit 0
PS0
x = Bit is unknown
PIC16F688
xxxx xxxx uuuu uuuu
0000 000x 0000 000x
1111 1111 1111 1111
POR, BOR
Value on
R/W-1
PS1
DS41203E-page 47
Value on
all other
Resets
R/W-1
PS0
bit 0