PIC16F688-I/STG Microchip Technology, PIC16F688-I/STG Datasheet - Page 122

• Manufacturer Part Number: PIC16F688-I/STG
• Description: IC PIC MCU FLASH 4KX14 14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/STG

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• For Use With: XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F688
11.3.1
External interrupt on RA2/INT pin is edge-triggered;
either rising if the INTEDG bit of the OPTION register is
set, or falling if the INTEDG bit is clear. When a valid
edge appears on the RA2/INT pin, the INTF bit of the
INTCON register is set. This interrupt can be disabled
by clearing the INTE control bit of the INTCON register.
The INTF bit must be cleared in software in the Inter-
rupt Service Routine before re-enabling this interrupt.
The RA2/INT interrupt can wake-up the processor from
Sleep if the INTE bit was set prior to going into Sleep.
The status of the GIE bit decides whether or not the
processor branches to the interrupt vector following
wake-up (0004h). See Section 11.6 “Power-Down
Mode (Sleep)” for details on Sleep and Figure 11-10
for timing of wake-up from Sleep through RA2/INT
interrupt.
FIGURE 11-7:
DS41203E-page 120
Note:
RA2/INT INTERRUPT
The ANSEL (91h) and CMCON0 (19h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
IOC-RA0
IOC-RA1
IOC-RA2
IOC-RA3
IOC-RA4
IOC-RA5
TMR1IE
TMR1IF
IOCA0
IOCA1
IOCA2
IOCA3
IOCA4
IOCA5
OSFIF
OSFIE
RCIF
RCIE
ADIF
ADIE
EEIE
TXIF
TXIE
C1IF
C1IE
C2IF
C2IE
EEIF
INTERRUPT LOGIC
RAIE
INTF
INTE
RAIF
PEIE
T0IF
T0IE
GIE
11.3.2
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF of the INTCON register bit. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON register. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
11.3.3
An input change on PORTA change sets the RAIF bit
of the INTCON register. The interrupt can be
enabled/disabled by setting/clearing the RAIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOCA register.
Note:
TIMER0 INTERRUPT
PORTA INTERRUPT
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
Wake-up (If in Sleep mode)
© 2009 Microchip Technology Inc.
Interrupt to CPU