PIC16F688-I/STG Microchip Technology, PIC16F688-I/STG Datasheet - Page 82
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PIC16F688-I/STG
Manufacturer Part Number
PIC16F688-I/STG
Description
IC PIC MCU FLASH 4KX14 14TSSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
Specifications of PIC16F688-I/STG
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-TSSOP
For Use With
XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F688T-ISL PDF datasheet #3
- PIC16F688T-ISL PDF datasheet #4
- PIC16F688T-ISL PDF datasheet #5
- Current page: 82 of 204
- Download datasheet (4Mb)
PIC16F688
9.1.2
To read a data memory location, the user must write
the address to the EEADR register, clear the EEPGD
control bit of the EECON1 register, and then set control
bit RD of the EECON1 register. The data is available in
the very next cycle, in the EEDAT register; therefore, it
can be read in the next instruction. EEDAT will hold this
value until another read or until it is written to by the
user (during a write operation).
EXAMPLE 9-1:
EXAMPLE 9-2:
DS41203E-page 80
BANKSEL EEADR
MOVLW
MOVWF
BCF
BSF
MOVF
BANKSEL EEADR
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL EECON1
BCF
BSF
BCF
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
SLEEP
BCF
DATA_EE_ADDR
EEADR
EECON1, EEPGD
EECON1, RD
EEDAT, W
READING THE DATA EEPROM
MEMORY
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDAT
EECON1, EEPGD
EECON1, WREN
INTCON, GIE
INTCON, GIE
$-2
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
DATA EEPROM READ
DATA EEPROM WRITE
;
;
;Data Memory
;Address to read
;Point to DATA
;memory
;EE Read
;W = EEDAT
;
;
;Data Memory Address to write
;
;Data Memory Value to write
;
;Point to DATA memory
;Enable writes
;Disable INTs.
;SEE AN576
;
;Write 55h
;
;Write AAh
;Set WR bit to begin write
;Enable INTs.
;Wait for interrupt to signal write complete
;Disable writes
9.1.3
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
WRITING TO THE DATA EEPROM
MEMORY
© 2009 Microchip Technology Inc.
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