AT89LP214-20XU Atmel, AT89LP214-20XU Datasheet - Page 75

• Manufacturer Part Number: AT89LP214-20XU
• Description: MCU 8051 2K FLASH 20MHZ 14-TSSOP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP214-20XU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Package: 14TSSOP
• Device Core: 8051
• Family Name: AT89
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 12
• Interface Type: SPI/UART
• Number Of Timers: 2
• Core: 8051
• Processor Series: AT89x
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 128 B
• Mounting Style: SMD/SMT
• Height: 1.05 mm
• Length: 5.1 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.4 V
• Width: 4.5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

23.8.5
3538E–MICRO–11/10
Serial Peripheral Interface
The Serial Peripheral Interface (SPI) is a byte-oriented full duplex synchronous serial communi-
cation channel. During In-System programming the programmer always acts as the SPI master
and the target device always acts as the SPI slave. The target device receives serial data on
MOSI and outputs serial data on MISO. The Programming Interface implements a standard
SPI Port with a fixed data order and For In-System programming, bytes are transferred MSB first
as shown in
CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge of
SCK. For more detailed timing information see
Figure 23-9. ISP Byte Sequence
Figure 23-10. Serial Programming Interface Timing
MISO
MOSI
SCK
SS
MOSI
MISO
SCK
Figure
t
SSE
23-9. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0,
t
SOE
7
7
t
SHSL
6
6
t
SCK
Data Sampled
t
5
5
t
SLSH
SR
t
SOV
Figure
4
4
t
SOH
23-10.
3
3
t
AT89LP213/214
SF
2
2
t
SIS
1
1
t
SIH
t
SSD
0
0
t
SOX
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