PIC12CE674-10I/P Microchip Technology, PIC12CE674-10I/P Datasheet - Page 124
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PIC12CE674-10I/P
Manufacturer Part Number
PIC12CE674-10I/P
Description
IC MCU OTP 2KX14 A/D&EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(3 pages)
4.PIC12CE673-10P.pdf
(14 pages)
5.PIC12CE673-10P.pdf
(12 pages)
Specifications of PIC12CE674-10I/P
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE674-10I/P
Manufacturer:
MICROCHIP
Quantity:
12 000
- PIC16F688T-ISL PDF datasheet
- PIC12CE673-10P PDF datasheet #2
- PIC12CE673-10P PDF datasheet #3
- PIC12CE673-10P PDF datasheet #4
- PIC12CE673-10P PDF datasheet #5
- Current page: 124 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
8.1
DS31008A-page 8-2
Introduction
PICmicro MCUs can have many sources of interrupt. These sources generally include one inter-
rupt source for each peripheral module, though some modules may generate multiple interrupts
(such as the USART module). The current interrupts are:
• INT Pin Interrupt (external interrupt)
• TMR0 Overflow Interrupt
• PORTB Change Interrupt (pins RB7:RB4)
• Comparator Change Interrupt
• Parallel Slave Port Interrupt
• USART Interrupts
• Receive Interrupt
• Transmit Interrupt
• A/D Conversion Complete Interrupt
• LCD Interrupt.
• Data EEPROM Write Complete Interrupt
• Timer1 Overflow Interrupt
• Timer2 Overflow Interrupt
• CCP Interrupt
• SSP Interrupt
There is a minimum of one register used in the control and status of the interrupts. This register
is:
• INTCON
Additionally, if the device has peripheral interrupts, then it will have registers to enable the periph-
eral interrupts and registers to hold the interrupt flag bits. Depending on the device, the registers
are:
• PIE1
• PIR1
• PIE2
• PIR2
We will generically refer to these registers as PIR and PIE. If future devices provide more inter-
rupt sources, they will be supported by additional register pairs, such as PIR3 and PIE3.
The Interrupt Control Register, INTCON, records individual flag bits for core interrupt requests.
It also has various individual enable bits and the global interrupt enable bit.
1997 Microchip Technology Inc.
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