PIC12CE674-10I/P Microchip Technology, PIC12CE674-10I/P Datasheet - Page 473
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PIC12CE674-10I/P
Manufacturer Part Number
PIC12CE674-10I/P
Description
IC MCU OTP 2KX14 A/D&EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(3 pages)
4.PIC12CE673-10P.pdf
(14 pages)
5.PIC12CE673-10P.pdf
(12 pages)
Specifications of PIC12CE674-10I/P
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE674-10I/P
Manufacturer:
MICROCHIP
Quantity:
12 000
- PIC16F688T-ISL PDF datasheet
- PIC12CE673-10P PDF datasheet #2
- PIC12CE673-10P PDF datasheet #3
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- PIC12CE673-10P PDF datasheet #5
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25.6
25.6.1
25.6.2
1997 Microchip Technology Inc.
V
DD
Note 1: Location of optional filter capacitor.
VLCDADJ
100k
130k
Charge Pump
External R-Ladder
Voltage Generation
2: These values are provided for design guidance only and should be optimized to the application by
(2)
(2)
nominal
10 A
the designer.
There are two methods for LCD voltage generation, internal charge pump, or external resistor
ladder.
The LCD charge pump is shown in
base voltage from the varying battery voltage. This regulator is adjustable through the range by
connecting a variable external resistor from VLCDADJ to ground. The potentiometer provides
contrast adjustment for the LCD. This base voltage is connected to V
The charge pump boosts V
pump is not operating, V
tion for charge pump capacitor and potentiometer values.
The LCD module can also use an external resistor ladder (R-Ladder) to generate the LCD volt-
ages.
bit must be cleared to use an external R-Ladder.
Figure 25-8:
V
V
DD
DD
Figure 25-8
V
0.47 F
LCD
10k*
3
Charge Pump and Resistor Ladder Block Diagram
(2)
shows external connections for static and 1/3 bias. The VGEN (LCDCON<4>)
(1)
V
0.47 F
LCD
LCD
10k
10k
LCD
2
3 will be internally tied to V
Charge Pump
(2)
(2)
1 into V
(2)
(1)
(1)
Figure
V
0.47 F
LCD
LCD
2 = 2 * V
1
25-8. The 1.0V - 2.3V regulator will establish a stable
(2)
10k*
LCD
Section 25. LCD
1 and V
DD
. See the Electrical Specifications sec-
LCD
(1)
0.47 F
3 = 3 * V
C1
5k
5k
(2)
(2)
LCD
C2
(2)
1 on the charge pump.
LCD
DS31025A-page 25-15
1. When the charge
External
connections for
internal charge
pump, VGEN = 1.
External
External
connections for
external R-ladder,
1/3 Bias,
VGEN = 0.
connections for
external R-ladder,
Static Bias,
VGEN = 0.
SLPEN
LCDEN
25
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