PIC12CE674-10I/P Microchip Technology, PIC12CE674-10I/P Datasheet - Page 305
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PIC12CE674-10I/P
Manufacturer Part Number
PIC12CE674-10I/P
Description
IC MCU OTP 2KX14 A/D&EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(3 pages)
4.PIC12CE673-10P.pdf
(14 pages)
5.PIC12CE673-10P.pdf
(12 pages)
Specifications of PIC12CE674-10I/P
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE674-10I/P
Manufacturer:
MICROCHIP
Quantity:
12 000
- PIC16F688T-ISL PDF datasheet
- PIC12CE673-10P PDF datasheet #2
- PIC12CE673-10P PDF datasheet #3
- PIC12CE673-10P PDF datasheet #4
- PIC12CE673-10P PDF datasheet #5
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- Download datasheet (3Mb)
17.4.6
17.4.7
1997 Microchip Technology Inc.
Multi-Master Mode
I
2
C Master Mode Support
In multi-master mode, the interrupt generation on the detection of the START and STOP condi-
tions allows the determination of when the bus is free. The STOP (P) and START (S) bits are
cleared from a reset or when the SSP module is disabled. Control of the I
when the P bit (SSPSTAT<4>) is set, or the bus is idle with both the S and P bits clear. When the
bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition
occurs.
In multi-master operation, the SDA line must be monitored, for arbitration, to see if the signal level
is the expected output level. This check is performed in hardware, with the result placed in the
BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
Master Mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by
setting the SSPEN bit. Once master mode is enabled, the user has six options.
1.
2.
3.
4.
5.
6.
Note:
Assert a start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and SCL.
Write to the SSPBUF register initiating transmission of data/address.
Generate a stop Condition on SDA and SCL.
Configure the I
Generate an acknowledge condition at the end of a received byte of data.
The SSP Module when configured in I
events. For instance: The user is not allowed to initiate a start condition, and imme-
diately write the SSPBUF register to imitate transmission before the START condi-
tion is complete. In this case the SSPBUF will not be written to, and the WCOL bit
will be set, indicating that a write to the SSPBUF did not occur.
2
C port to receive data.
Preliminary
Section 17. MSSP
2
C Master Mode does not allow queueing of
2
DS31017A-page 17-29
C bus may be taken
17
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