PIC12CE674-10I/P Microchip Technology, PIC12CE674-10I/P Datasheet - Page 349
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PIC12CE674-10I/P
Manufacturer Part Number
PIC12CE674-10I/P
Description
IC MCU OTP 2KX14 A/D&EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(3 pages)
4.PIC12CE673-10P.pdf
(14 pages)
5.PIC12CE673-10P.pdf
(12 pages)
Specifications of PIC12CE674-10I/P
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE674-10I/P
Manufacturer:
MICROCHIP
Quantity:
12 000
- PIC16F688T-ISL PDF datasheet
- PIC12CE673-10P PDF datasheet #2
- PIC12CE673-10P PDF datasheet #3
- PIC12CE673-10P PDF datasheet #4
- PIC12CE673-10P PDF datasheet #5
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18.4.3
18.4.3.1
1997 Microchip Technology Inc.
(RX/DT pin)
(RX/DT pin)
baud CLK
baud CLK
Sampling
Device Exceptions
x16 CLK
x16 CLK
RX
RX
The data on the RX/DT pin is sampled three times by a majority detect circuit to determine if a
high or a low level is present at the RX pin.
circuit. The sampling operates the same regardless of the state of the BRGH bit, only the source
of the x16 clock is different.
Figure 18-6:
All new devices will use the sampling scheme shown in
tion to the above sampling scheme are:
• PIC16C63
• PIC16C65
• PIC16C65A
• PIC16C73
• PIC16C73A
• PIC16C74
• PIC16C74A
These devices have a sampling circuitry that works as follows. If the BRGH bit (TXSTA<2>) is
clear (i.e., at the low baud rates), the sampling is done on the seventh, eighth and ninth falling
edges of a x16 clock
is done on the 3 clock edges preceding the second rising edge after the first falling edge of a x4
clock
Figure 18-7:
1
1
(Figure 18-8
2
2
3
3
4
4
RX Pin Sampling Scheme, BRGH = 0 or BRGH = 1
RX Pin Sampling Scheme (BRGH = 0)
and
(Figure
5
5
Figure
6
6
18-7). If bit BRGH is set (i.e., at the high baud rates), the sampling
18-9).
7
7
Samples
Samples
8
8
9
9
Start bit
Start bit
Figure 18-6
10
10
Section 18. USART
11
11
Baud CLK for all but start bit
Baud CLK for all but start bit
12
12
Figure
shows the waveform for the sampling
13
13
18-6. Devices that have an excep-
14
14
15
15
16
16
DS31018A-page 18-13
1
1
2
2
Bit0
Bit0
3
3
18
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