DSPIC33FJ12GP202-I/SS Microchip Technology, DSPIC33FJ12GP202-I/SS Datasheet - Page 230

• Manufacturer Part Number: DSPIC33FJ12GP202-I/SS
• Description: IC DSPIC MCU/DSP 12K 28SSOP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12GP202-I/SS

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28SSOP
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ12GP201/202
Revision C (June 2008)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in the following table.
TABLE 22-1:
DS70264C-page 228
“High-Performance, 16-Bit Digital
Signal Controllers”
Section 1.0 “Device Overview”
Section 3.0 “Memory Organization”
Section 4.0 “Flash Program
Memory”
Section 5.0 “Resets”
Section 7.0 “Oscillator
Configuration”
Section 8.0 “Power-Saving
Features”
Section Name
MAJOR SECTION UPDATES
Added SSOP to list of available 28-pin packages (see “Packaging:” and
Table 1).
Added External Interrupts column to Remappable Peripherals in the
Controller Families table and Note 2 (see Table 1).
Added Note 1 to all pin diagrams, which references RPn pin usage by
remappable peripherals (see “Pin Diagrams”).
Changed Capture Input pin names from IC0-IC1 to IC1-IC2 and updated
description for AV
Added SFR definitions (ACCAL, ACCAH, ACCAU, ACCBL, ACCBH, and
ACCBU) to the CPU Core Register Map (see Table 3-1).
Updated Reset value for CORCON SFR (see Table 3-1).
Updated Reset values for the following SFRs: IPC1, IPC2-ICP7, IPC16, and
INTTREG (see Table 3-4).
The following changes were made to the ADC1 Register Maps:
• Updated the bit range for AD1CON3 from ADCS<5:0> to ADCS<7:0>)
• Updated Reset value for PLLFBD SFR (see Table 3-19).
• Added Bit 6 (PCFG7) and Bit 7 (PCFG6) names to AD1PCFGL
• Added Bit 6 (CSS7) and Bit 7 (CSS6) names to AD1CSSL (see Table 3-
• Changed Bit 5 and Bit 4 in AD1CSSL to unimplemented (see Table 3-14).
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 3-19).
Updated Section 4.3 “Programming Operations” with programming time
formula.
Entire section was replaced to maintain consistency with other dsPIC33F
data sheets.
Removed the first sentence of the third clock source item (External Clock) in
Section 7.1.1.2 “Primary”
Updated the default bit values for DOZE and FRCDIV in the Clock Divisor
Register (see Register 7-2).
Added the center frequency in the OSCTUN register for the FRC Tuning bits
(TUN<5:0>) value 011111 and updated the center frequency for bits value
011110 (see Register 7-4)
Added the following two registers:
• PMD1: Peripheral Module Disable Control Register 1
• PMD2: Peripheral Module Disable Control Register 2
(see Table 3-14 and Table 3-15).
(Table 3-14).
14).
Preliminary
DD
(see Table 1-1).
Update Description
© 2008 Microchip Technology Inc.