ATTINY861-20SU Atmel, ATTINY861-20SU Datasheet - Page 194

• Manufacturer Part Number: ATTINY861-20SU
• Description: IC MCU AVR 8K FLASH 20MHZ 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY861-20SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: USI
• Total Internal Ram Size: 512Byte
• # I/os (max): 16
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 11-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SOIC
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.8
Figure 19-6. Parallel Programming Timing, Including some General Timing Requirements
Figure 19-7. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
194
PAGEL/BS1
(DATA, XA0, XA1/BS2, PAGEL/BS1)
XA1/BS2
XTAL1
DATA
XA0
Parallel Programming Characteristics
The timing requirements shown in
ATtiny261/461/861
ADDR0 (Low Byte)
Data & Contol
LOAD ADDRESS
(LOW BYTE)
RDY/BSY
XTAL1
WR
Figure 19-6
t
t
BVPH
DVXH
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
(i.e., t
DVXH
t
XHXL
, t
t
XHXL
XLXH
t
t
t
t
, and t
XLDX
PLBX
XLWL
PLWL
XLDX
(HIGH BYTE)
LOAD DATA
t
BVWL
) also apply to loading operation.
DATA (High Byte)
t
WLWH
WLRL
t
WLBX
LOAD ADDRESS
(LOW BYTE)
ADDR1 (Low Byte)
2588E–AVR–08/10
t
WLRH