AT91SAM7S161-AU Atmel, AT91SAM7S161-AU Datasheet - Page 246
![IC MCU ARM7 16KB FLASH 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT91SAM7S161-AU
Manufacturer Part Number
AT91SAM7S161-AU
Description
IC MCU ARM7 16KB FLASH 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S161-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
AT91SAM7S161-AU
Manufacturer:
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Figure 27-5. Input Glitch Filter Timing
27.4.10
Figure 27-6. Input Change Interrupt Timings
27.5
246
if PIO_IFSR = 0
if PIO_IFSR = 1
Read PIO_ISR
PIO_PDSR
PIO_PDSR
Pin Level
Pin Level
PIO_ISR
I/O Lines Programming Example
AT91SAM7S Series Preliminary
MCK
Input Change Interrupt
MCK
The PIO Controller can be programmed to generate an interrupt when it detects an input change
on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable
Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the
input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask
Register). As Input change detection is possible only by comparing two successive samplings of
the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is
available, regardless of the configuration of the I/O line, i.e. configured as an input only, con-
trolled by the PIO Controller or assigned to a peripheral function.
When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt
Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt
line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to gen-
erate a single interrupt signal to the Advanced Interrupt Controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that
all the interrupts that are pending when PIO_ISR is read must be handled.
The programing example as shown in
configuration.
1 cycle
• 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain,
with pull-up resistor
1 cycle
APB Access
up to 1.5 cycles
Table 27-1
1 cycle
up to 2.5 cycles
2 cycles
below is used to define the following
APB Access
6175K–ATARM–30-Aug-10
up to 2 cycles
1 cycle
1 cycle
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