AT91SAM7S161-AU Atmel, AT91SAM7S161-AU Datasheet - Page 320
AT91SAM7S161-AU
Manufacturer Part Number
AT91SAM7S161-AU
Description
IC MCU ARM7 16KB FLASH 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S161-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Figure 30-7. Master Write with Multiple Data Byte
Figure 30-8. Master Write with One Byte Internal Address and Multiple Data Bytes
30.7.5
320
TXCOMP
TXCOMP
TXRDY
TXRDY
TWD
TWD
Write THR (Data n)
AT91SAM7S Series Preliminary
Master Receiver Mode
S
Write THR (Data n)
S
DADR
DADR
Figure 30-6. Master Write with One Data Byte
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
W
W
TXCOMP
A
TXRDY
TWD
IADR(7:0)
A
Write THR (DATA)
S
Write THR (Data n+1)
DATA n
A
DADR
DATA n
Write THR (Data n+1)
A
W
A
A
Write THR (Data n+x)
DATA n+5
Last data sent
DATA
Write THR (Data n+x)
DATA n+5
Last data sent
A
(ACK received and TXRDY = 1)
A
A
DATA n+x
STOP sent automaticaly
(ACK received and TXRDY = 1)
(ACK received and TXRDY = 1)
P
STOP sent automaticaly
DATA n+x
STOP sent automaticaly
Figure
6175K–ATARM–30-Aug-10
A
30-9. When the
A
P
P
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