ATMEGA169P-16MCH Atmel, ATMEGA169P-16MCH Datasheet - Page 258

MCU AVR 16KB FLASH 16MHZ 64-VQFN

ATMEGA169P-16MCH

Manufacturer Part Number
ATMEGA169P-16MCH
Description
MCU AVR 16KB FLASH 16MHZ 64-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA169P-16MCH

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
24.7
24.7.1
24.8
24.9
8018P–AVR–08/10
On-chip Debug Related Register in I/O Memory
Using the JTAG Programming Capabilities
Bibliography
OCDR – On-chip Debug Register
The OCDR Register provides a communication channel from the running program in the micro-
controller to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the register has been written. When the CPU reads the OCDR Register the
7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the
IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR
Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and
TDO. These are the only pins that need to be controlled/observed to perform JTAG program-
ming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse
must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the
JTAG Test Access Port. See
The JTAG programming capability supports:
• Flash programming and verifying.
• EEPROM programming and verifying.
• Fuse programming and verifying.
• Lock bit programming and verifying.
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are
programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a
security feature that ensures no back-door exists for reading out the content of a secured
device.
The details on programming through the JTAG interface and programming specific JTAG
instructions are given in the section
For more information about general Boundary-scan, the following literature can be consulted:
• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan
• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992.
Bit
0x31 (0x51)
Read/Write
Initial Value
Architecture, IEEE, 1993.
MSB/IDRD
R/W
7
0
R/W
6
0
”Boundary-scan Related Register in I/O Memory” on page
”Programming via the JTAG Interface” on page
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
ATmega169P
R/W
1
0
LSB
R/W
0
0
316.
279.
OCDR
258

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