PIC18LF27J53-I/SO Microchip Technology, PIC18LF27J53-I/SO Datasheet - Page 396
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PIC18LF27J53-I/SO
Manufacturer Part Number
PIC18LF27J53-I/SO
Description
IC PIC MCU 128KB FLASH 28SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18LF27J53-I/SO
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
SOIC
Supply Voltage Range
1.8V To 3.6V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 396 of 586
- Download datasheet (6Mb)
PIC18F47J53 FAMILY
23.5.1.1
The ACTVIF bit cannot be cleared immediately after
the USB module wakes up from Suspend mode or
while the USB module is suspended. A few clock
cycles are required to synchronize the internal hard-
ware state machine before the ACTVIF bit can be
cleared by firmware. Clearing the ACTVIF bit before
the internal hardware is synchronized may not have an
effect on the value of ACTVIF. Additionally, if the USB
module uses the clock from the 96 MHz PLL source,
then after clearing the SUSPND bit, the USB module
EXAMPLE 23-1:
DS39964B-page 396
Assembly:
LOOP:
DONE:
C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }
BCF
BTFSS
BRA
BCF
BRA
Bus Activity Detect Interrupt Bit
(ACTVIF)
UCON, SUSPND
UIR, ACTVIF
DONE
UIR, ACTVIF
LOOP
CLEARING ACTVIF BIT (UIR<2>)
Preliminary
may not be immediately operational while waiting for
the 96 MHz PLL to lock. The application code should
clear the ACTVIF flag as provided in Example 23-1.
Note:
Only one ACTVIF interrupt is generated
when resuming from the USB bus Idle con-
dition. If user firmware clears the ACTVIF
bit, the bit will not immediately become set
again, even when there is continuous bus
traffic. Bus traffic must cease long enough
to generate another IDLEIF condition
before another ACTVIF interrupt can be
generated.
2010 Microchip Technology Inc.
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