PIC18LF27J53-I/SO Microchip Technology, PIC18LF27J53-I/SO Datasheet - Page 452
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PIC18LF27J53-I/SO
Manufacturer Part Number
PIC18LF27J53-I/SO
Description
IC PIC MCU 128KB FLASH 28SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18LF27J53-I/SO
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
SOIC
Supply Voltage Range
1.8V To 3.6V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 452 of 586
- Download datasheet (6Mb)
PIC18F47J53 FAMILY
REGISTER 28-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ACCESS FC0h)
TABLE 28-3:
DS39964B-page 452
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
REGSLP
R/W-1
Name
2:
This bit has no effect if the Configuration bit, WDTEN, is enabled.
Not available on devices where the on-chip voltage regulator is disabled (“LF” devices).
REGSLP: Voltage Regulator Low-Power Operation Enable bit
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator is active even in Sleep mode
LVDSTAT: Low-Voltage Detect Status bit
1 = V
0 = V
ULPLVL: Ultra Low-Power Wake-up Output bit (not valid unless ULPEN = 1)
1 = Voltage on RA0 > ~0.5V
0 = Voltage on RA0 < ~0.5V
VBGOE: Band Gap Reference Voltage (VBG) Output Enable bit
1 = Band gap reference output is enabled on pin RA1
0 = Band gap reference output is disabled
DS: Deep Sleep Wake-up Status bit (used in conjunction with RCON, POR and BOR bits to determine
Reset source)
1 = If the last exit from Reset was caused by a normal wake-up from Deep Sleep
0 = If the last exit from Reset was not due to a wake-up from Deep Sleep
ULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = Ultra low-power wake-up module is enabled; ULPLVL bit indicates the comparator output
0 = Ultra low-power wake-up module is disabled
ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit
1 = Ultra low-power wake-up current sink is enabled (if ULPEN = 1)
0 = Ultra low-power wake-up current sink is disabled
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
LVDSTAT
REGSLP
SUMMARY OF WATCHDOG TIMER REGISTERS
IPEN
Bit 7
R-x
DDCORE
DDCORE
(2)
> 2.45V nominal
< 2.45V nominal
(2)
LVDSTAT
W = Writable bit
‘1’ = Bit is set
Bit 6
ULPLVL
—
R-x
ULPLVL
Bit 5
CM
VBGOE
R/W-0
Preliminary
(2)
VBGOE
Bit 4
RI
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
DS
(2)
Bit 3
TO
DS
(1)
ULPEN
R/W-0
ULPEN
Bit 2
PD
2010 Microchip Technology Inc.
x = Bit is unknown
ULPSINK
R/W-0
ULPSINK
Bit 1
POR
SWDTEN
SWDTEN
R/W-0
Bit 0
BOR
bit 0
(1)
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