ATMEGA644P-20MQ Atmel, ATMEGA644P-20MQ Datasheet - Page 168
ATMEGA644P-20MQ
Manufacturer Part Number
ATMEGA644P-20MQ
Description
MCU AVR 64K FLASH 20MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA164P-20AU.pdf
(439 pages)
Specifications of ATMEGA644P-20MQ
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.5
15.5.1
8011O–AVR–07/10
Register Description
SPCR – SPI Control Register
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
marized below:
Table 15-3.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 15-4.
Bit
0x2C (0x4C)
Read/Write
Initial Value
CPOL
CPHA
CPOL Functionality
CPHA Functionality
0
1
0
1
SPIE
R/W
7
0
Figure 15-3
SPE
R/W
6
0
and
DORD
R/W
5
0
Figure 15-4
Figure 15-3
Leading Edge
Leading Edge
MSTR
Sample
Falling
R/W
Rising
Setup
4
0
for an example. The CPOL functionality is sum-
ATmega164P/324P/644P
and
CPOL
R/W
3
0
Figure 15-4
CPHA
R/W
2
0
for an example. The CPOL
SPR1
R/W
1
0
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
SPR0
R/W
0
0
SPCR
168
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