PIC24FJ256GB106T-I/PT Microchip Technology, PIC24FJ256GB106T-I/PT Datasheet - Page 128
![IC PIC MCU FLASH 256K 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC24FJ256GB106T-I/PT
Manufacturer Part Number
PIC24FJ256GB106T-I/PT
Description
IC PIC MCU FLASH 256K 64-TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA106-IPT.pdf
(52 pages)
2.PIC24FJ64GB106-IPT.pdf
(16 pages)
3.PIC24FJ64GB106-IPT.pdf
(352 pages)
Specifications of PIC24FJ256GB106T-I/PT
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
256KB (85.5K x 24)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUMA240014 - MODULE PLUG-IN PIC24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC24FJ256GB106T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ256GB106T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC24FJ128GA106-IPT PDF datasheet
- PIC24FJ64GB106-IPT PDF datasheet #2
- PIC24FJ64GB106-IPT PDF datasheet #3
- Current page: 128 of 352
- Download datasheet (3Mb)
PIC24FJ256GB110 FAMILY
8.5
Because of the timing requirements imposed by USB,
an internal clock of 48 MHz is required at all times while
the USB module is enabled. Since this is well beyond
the maximum CPU clock speed, a method is provided
to internally generate both the USB and system clocks
from a single oscillator source. PIC24FJ256GB110
family devices use the same clock structure as other
PIC24FJ devices, but include a two-branch PLL system
to generate the two clock signals.
The USB PLL block is shown in Figure 8-2. In this
system, the input from the Primary Oscillator is divided
down by a PLL prescaler to generate a 4 MHz output.
This is used to drive an on-chip 96 MHz PLL frequency
multiplier to drive the two clock branches. One branch
uses a fixed divide-by-2 frequency divider to generate
the 48 MHz USB clock. The other branch uses a fixed
divide-by-3 frequency divider and configurable PLL
prescaler/divider to generate a range of system clock
frequencies. The CPDIV bits select the system clock
speed; available clock options are listed in Table 8-2.
The USB PLL prescaler does not automatically sense
the incoming oscillator frequency. The user must man-
ually configure the PLL divider to generate the required
4 MHz output, using the PLLDIV<2:0> Configuration
bits. This limits the choices for Primary Oscillator fre-
quency to a total of 8 possibilities, shown in Table 8-3.
FIGURE 8-2:
DS39897C-page 128
(4 MHz or
8 MHz)
Input from
POSC
Input from
FRC
Oscillator Modes and USB
Operation
FNOSC<2:0>
USB PLL BLOCK
12
10
6
5
4
3
2
1
PLLDIV<2:0>
111
110
101
100
011
010
001
000
4 MHz
PLLDIS
96 MHz
PLL
TABLE 8-2:
TABLE 8-3:
Input Oscillator
Frequency
2
3
MCU Clock Division
48 MHz
40 MHz
24 MHz
20 MHz
16 MHz
12 MHz
8 MHz
4 MHz
(CPDIV<1:0>)
None (00)
32 MHz
2 (01)
4 (10)
8 (11)
SYSTEM CLOCK OPTIONS
DURING USB OPERATION
VALID PRIMARY OSCILLATOR
CONFIGURATIONS FOR USB
OPERATIONS
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
ECPLL, XTPLL
ECPLL, XTPLL
Clock Mode
ECPLL
ECPLL
2009 Microchip Technology Inc.
8
4
2
1
CPDIV<1:0>
11
10
01
00
Clock Frequency
Microcontroller
PLL Output
for System Clock
48 MHz Clock
for USB Module
32 MHz
16 MHz
8 MHz
4 MHz
(PLLDIV<2:0>)
PLL Division
12 (111)
10 (110)
6 (101)
5 (100)
4 (011)
3 (010)
2 (001)
1 (000)
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