PIC24FJ256GB106T-I/PT Microchip Technology, PIC24FJ256GB106T-I/PT Datasheet - Page 220
![IC PIC MCU FLASH 256K 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC24FJ256GB106T-I/PT
Manufacturer Part Number
PIC24FJ256GB106T-I/PT
Description
IC PIC MCU FLASH 256K 64-TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA106-IPT.pdf
(52 pages)
2.PIC24FJ64GB106-IPT.pdf
(16 pages)
3.PIC24FJ64GB106-IPT.pdf
(352 pages)
Specifications of PIC24FJ256GB106T-I/PT
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
256KB (85.5K x 24)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUMA240014 - MODULE PLUG-IN PIC24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC24FJ256GB106T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ256GB106T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC24FJ128GA106-IPT PDF datasheet
- PIC24FJ64GB106-IPT PDF datasheet #2
- PIC24FJ64GB106-IPT PDF datasheet #3
- Current page: 220 of 352
- Download datasheet (3Mb)
PIC24FJ256GB110 FAMILY
18.5.3
1.
2.
3.
4.
5.
6.
7.
DS39897C-page 220
Note:
Follow the procedure described in Section 18.5.1
“Enable Host Mode and Discover a Connected
Device” and Section 18.5.2 “Complete a Con-
trol Transaction to a Connected Device” to
discover and configure a device.
To enable transmit and receive transfers with
handshaking enabled, write 1Dh to U1EP0. If
the target device is a low-speed device, also set
the LSPD bit (U1EP0<7>). If you want the hard-
ware to automatically retry indefinitely if the
target device asserts a NAK on the transfer,
clear
(U1EP0<6>).
Set up the BD for the current (EVEN or ODD) Tx
EP0 to transfer up to 64 bytes.
Set the USB device address of the target device
in the address register (U1ADDR<6:0>).
Write an OUT token to the desired endpoint to
U1TOK. This triggers the module’s transmit
state machines to begin transmitting the token
and the data.
Wait for the Transfer Done Interrupt Flag,
TRNIF. This indicates that the BD has been
released back to the microprocessor, and the
transfer has completed. If the retry disable bit is
set, the handshake (ACK, NAK, STALL or
ERROR (0Fh)) is returned in the BD PID field. If
a STALL interrupt occurs, the pending packet
must be dequeued and the error condition in the
target device cleared. If a detach interrupt
occurs (SE0 for more than 2.5 µs), then the
target has detached (U1IR<0> is set).
Once the transfer done interrupt occurs (TRNIF
is set), the BD can be examined and the next
data packet queued by returning to step 2.
SEND A FULL-SPEED BULK DATA
TRANSFER TO A TARGET DEVICE
the
USB speed, transceiver and pull-ups
should only be configured during the
module setup phase. It is not recom-
mended to change these settings while
the module is enabled.
Retry
Disable
bit,
RETRYDIS
Session Request Protocol (SRP). Software may do this
18.6
18.6.1
An OTG A-device may decide to power down the V
supply when it is not using the USB link through the
by clearing VBUSON (U1OTGCON<3>). When the V
supply is powered down, the A-device is said to have
ended a USB session.
An OTG A-device or Embedded Host may repower the
V
OTG B-device may also request that the OTG A-device
repower the V
is accomplished via Session Request Protocol (SRP).
Prior to requesting a new session, the B-device must
first check that the previous session has definitely
ended. To do this, the B-device must check for two
conditions:
1. V
2. Both D+ and D- have been low for at least 2 ms.
The B-device will be notified of condition 1 by the
SESENDIF (U1OTGIR<2>) interrupt. Software will
have to manually check for condition 2.
The B-device may aid in achieving condition 1 by dis-
charging the V
may do this by setting VBUSDIS (U1OTGCON<0>).
After these initial conditions are met, the B-device may
begin requesting the new session. The B-device begins
by pulsing the D+ data line. Software should do this by
setting DPPULUP (U1OTGCON<7>). The data line
should be held high for 5 to 10 ms.
The B-device then proceeds by pulsing the V
supply. Software should do this by setting PUVBUS
(U1CNFG2<4>). When an A-device detects SRP sig-
naling (either via the ATTACHIF (U1IR<6>) interrupt or
via the SESVDIF (U1OTGIR<3>) interrupt), the
A-device must restore the V
VBUSON (U1OTGCON<3>), or by setting the I/O port
controlling the external power source.
The B-device should not monitor the state of the V
supply while performing V
B-device does detect that the V
restored (via the SESVDIF (U1OTGIR<3>) interrupt),
the B-device must re-connect to the USB link by pulling
up D+ or D- (via the DPPULUP or DMPULUP).
The A-device must complete the SRP by driving USB
Reset signaling.
BUS
Note:
BUS
supply at any time (initiate a new session). An
supply is below the Session Valid voltage and
OTG Operation
SESSION REQUEST PROTOCOL
(SRP)
When the A-device powers down the V
supply, the B-device must disconnect its
pull-up resistor from power. If the device is
self-powered, it can do this by clearing
DPPULUP
DMPULUP (U1OTGCON<6>).
BUS
BUS
supply (initiate a new session). This
supply through a resistor. Software
2009 Microchip Technology Inc.
BUS
(U1OTGCON<7>)
BUS
supply pulsing. When the
supply by either setting
BUS
supply has been
BUS
and
BUS
BUS
BUS
BUS
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