PIC16LC926-I/PT Microchip Technology, PIC16LC926-I/PT Datasheet - Page 62
![IC MCU CMOS 20MHZ 8K W/LCD64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC16LC926-I/PT
Manufacturer Part Number
PIC16LC926-I/PT
Description
IC MCU CMOS 20MHZ 8K W/LCD64TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC926-I/PT
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
OTP
Ram Size
336 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC16C
No. Of I/o's
25
Ram Memory Size
336Byte
Cpu Speed
20MHz
No. Of Timers
3
Interface
I2C, SPI
Embedded Interface Type
I2C, SPI
Rohs Compliant
Yes
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
336 B
Interface Type
I2C, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LC926-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC16LC926-I/PT
Manufacturer:
MIC
Quantity:
20 000
PIC16C925/926
REGISTER 9-2:
DS39544A-page 60
bit 7
bit 6
bit 5
bit 4
bit 3-0
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
bit 7
WCOL: Write Collision Detect bit
1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while SSPBUF is holding previous data. Data in SSPSR is lost on overflow.
0 = No overflow
In I
1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a “don’t care” in transmit
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
When enabled, these pins must be properly configured as input or output.
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
When enabled, these pins must be properly configured as input or output.
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin (SS pin control enabled)
0101 = SPI Slave mode, clock = SCK pin (SS pin control disabled, SS can be used as I/O pin)
0110 = I
0111 = I
1011 = I
1110 = I
1111 = I
1000, 1001, 1010, 1100, 1101 = reserved
Legend:
R = Readable bit
- n = Value at POR
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
WCOL
R/W-0
2
2
2
Overflow only occurs in Slave mode. The user must read the SSPBUF, even if only transmitting data,
to avoid setting overflows. In Master mode, the overflow bit is not set since each operation is initiated
by writing to the SSPBUF register. (Must be cleared in software.)
C mode:
mode. (Must be cleared in software.)
C mode:
C mode:
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C firmware controlled Master mode (slave idle)
C firmware controlled Master mode, 7-bit address with START and STOP bit interrupts enabled
C firmware controlled Master mode, 10-bit address with START and STOP bit interrupts enabled
SSPOV
R/W-0
W = Writable bit
’1’ = Bit is set
SSPEN
R/W-0
Preliminary
OSC
OSC
OSC
/4
/16
/64
R/W-0
CKP
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
SSPM3
R/W-0
SSPM2
R/W-0
2001 Microchip Technology Inc.
x = Bit is unknown
SSPM1
R/W-0
SSPM0
R/W-0
bit 0