AT90CAN64-16AUR Atmel, AT90CAN64-16AUR Datasheet - Page 174

MCU AVR 64K FLASH 16MHZ 64TQFP

AT90CAN64-16AUR

Manufacturer Part Number
AT90CAN64-16AUR
Description
MCU AVR 64K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Datasheet

Specifications of AT90CAN64-16AUR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
4 KB
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90CAN64-16AUR
Manufacturer:
Atmel
Quantity:
10 000
174
AT90CAN32/64/128
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
marized below:
Table 16-2.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 16-3.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the clk
the following table:
Table 16-4.
SPI2X
0
0
0
0
1
1
1
1
CPOL
CPHA
CPOL Functionality
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
0
1
0
1
Figure 16-3
SPR1
0
0
1
1
0
0
1
1
and
Figure 16-4
Figure 16-3
Leading Edge
Leading Edge
Sample
Falling
Rising
Setup
SPR0
0
1
0
1
0
1
0
1
for an example. The CPOL functionality is sum-
and
Figure 16-4
SCK Frequency
f
f
f
f
f
f
f
f
clkio
clkio
clkio
clkio
clkio
clkio
clkio
clkio
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
IO
for an example. The CPOL
frequency f
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
clkio
7679H–CAN–08/08
is shown in

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