AT90CAN64-16AUR Atmel, AT90CAN64-16AUR Datasheet - Page 248
AT90CAN64-16AUR
Manufacturer Part Number
AT90CAN64-16AUR
Description
MCU AVR 64K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Datasheet
1.AT90CAN32-16AUR.pdf
(428 pages)
Specifications of AT90CAN64-16AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
4 KB
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.7
19.7.1
19.7.2
248
Error Management
AT90CAN32/64/128
Fault Confinement
Error Types
The CAN channel may be in one of the three following states:
For fault confinement, a transmit error counter (TEC) and a receive error counter (REC) are
implemented. BOFF and ERRP bits give the information of the state of the CAN channel. Setting
BOFF to one may generate an interrupt.
Figure 19-12. Line Error Mode
Note:
• Error active (default):
• Error passive:
• Bus off:
• BERR: Bit error. The bit value which is monitored is different from the bit value sent.
• SERR: Stuff error. Detection of more than five consecutive bit with the same polarity.
• CERR: CRC error (Rx only). The receiver performs a CRC check on every destuffed received
• FERR: Form error. The form error results from one (or more) violations of the fixed form of
The CAN channel takes part in bus communication and can send an active error frame when
the CAN macro detects an error.
The CAN channel cannot send an active error frame. It takes part in bus communication, but
when an error is detected, a passive error frame is sent. Also, after a transmission, an error
passive unit will wait before initiating further transmission.
The CAN channel is not allowed to have any influence on the bus.
message from the start of frame up to the data field. If this checking does not match with the
destuffed CRC field, an CRC error is set.
the following bit fields:
– CRC delimiter
– acknowledgement delimiter
Note:
More than one REC/TEC change may apply during a given message transfer.
Exceptions:
- Recessive bit sent monitored as dominant bit during the arbitration field and the acknowl-
edge slot.
- Detecting a dominant bit during the sending of an error frame.
ERRP = 1
BOFF = 0
Passive
Error
TEC > 127 or
REC > 127
ERRP = 0
BOFF = 0
TEC < 127 and
REC < 127
interrupt - BOFFIT
TEC > 255
Active
Error
Reset
ERRP = 0
BOFF = 1
of 11 consecutive
128 occurrences
recessive bit
Bus
Off
7679H–CAN–08/08
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