ATMEGA128A-MUR Atmel, ATMEGA128A-MUR Datasheet - Page 194
![MCU AVR 128K FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128A-MUR
Manufacturer Part Number
ATMEGA128A-MUR
Description
MCU AVR 128K FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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20.9.3
8151H–AVR–02/11
UCSRnB - USARTn Control and Status Register B
• Bit 3 – DORn: Data OverRun
This bit is set if a Data OverRun condition is detected. A data overrun occurs when the receive
buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this
bit to zero when writing to UCSRnA.
• Bit 2 – UPEn: Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received and the
parity checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer
(UDRn) is read. Always set this bit to zero when writing to UCSRnA.
• Bit 1 – U2Xn: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-
chronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-
bling the transfer rate for asynchronous communication.
• Bit 0 – MPCMn: Multi-Processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to
one, all the incoming frames received by the USART Receiver that do not contain address infor-
mation will be ignored. The transmitter is unaffected by the MPCMn setting. For more detailed
information see
• Bit 7 – RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt
will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is writ-
ten to one and the RXC bit in UCSRnA is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn flag. A USARTn Transmit Complete inter-
rupt will be generated only if the TXCIEn bit is written to one, the global interrupt flag in SREG is
written to one and the TXCn bit in UCSRnA is set.
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn flag. A Data Register Empty interrupt will
be generated only if the UDRIEn bit is written to one, the global interrupt flag in SREG is written
to one and the UDREn bit in UCSRnA is set.
• Bit 4 – RXENn: Receiver Enable
Writing this bit to one enables the USARTn Receiver. The Receiver will override normal port
operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn and UPEn flags.
Bit
Read/Write
Initial Value
RXCIEn
“Multi-processor Communication Mode” on page
R/W
7
0
TXCIEn
R/W
6
0
UDRIEn
R/W
5
0
RXENn
R/W
4
0
TXENn
R/W
3
0
UCSZn2
R/W
2
0
191.
RXB8n
ATmega128A
R
1
0
TXB8n
R/W
0
0
UCSRnB
194
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