ATMEGA128A-MUR Atmel, ATMEGA128A-MUR Datasheet - Page 83
![MCU AVR 128K FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128A-MUR
Manufacturer Part Number
ATMEGA128A-MUR
Description
MCU AVR 128K FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12.3.6
8151H–AVR–02/11
Alternate Functions of Port F
Table 12-16. Overriding Signals for Alternate Functions in PE3:PE0
The Port F has an alternate function as analog input for the ADC as shown in
some Port F pins are configured as outputs, it is essential that these do not switch when a con-
version is in progress. This might corrupt the result of the conversion. In ATmega103
compatibility mode Port F is input only. If the JTAG interface is enabled, the pull-up resistors on
pinspF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs.
Table 12-17. Port F Pins Alternate Functions
• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Reg-
ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When
the JTAG interface is enabled, this pin can not be used as an I/O pin.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Port Pin
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
Alternate Function
ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select)
ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)
ADC3 (ADC input channel 3)
ADC2 (ADC input channel 2)
ADC1 (ADC input channel 1)
ADC0 (ADC input channel 0)
PE3/AIN1/OC3A
0
0
0
0
OC3B ENABLE
OC3B
0
0
0
AIN1 INPUT
PE2/AIN0/XCK0
0
0
0
0
UMSEL0
XCK0 OUTPUT
0
0
XCK0 INPUT
AIN0 INPUT
.
.
PE1/PDO/TXD0
TXEN0
0
TXEN0
1
TXEN0
TXD0
0
0
–
–
ATmega128A
0
–
PE0/PDI/RXD0
RXEN0
PORTE0 • PUD
RXEN0
0
0
0
0
RXD0
Table
12-17. If
83
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