PIC18LF2420-I/SP Microchip Technology, PIC18LF2420-I/SP Datasheet - Page 216

• Manufacturer Part Number: PIC18LF2420-I/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2420-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/USART
• On-chip Adc: 10-chx10-bit
• Number Of Timers: 4
• Core: PIC
• Processor Series: PIC18LF
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 768 B
• Data Rom Size: 256 B
• Mounting Style: Through Hole
• Height: 3.3 mm
• Length: 34.67 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2420/2520/4420/4520
FIGURE 18-7:
TABLE 18-6:
18.2.4
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RX/DT line while the
EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event con-
sists of a high-to-low transition on the RX/DT line. (This
coincides with the start of a Sync Break or a Wake-up
Signal character for the LIN protocol.)
DS39631E-page 214
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
Note:
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RX input.
causing the OERR (overrun) bit to be set.
Reserved in 28-pin devices; always maintain these bits clear.
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
EUSART Receive Register
GIE/GIEH PEIE/GIEL
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
ABDOVF
PSPIE
PSPIP
PSPIF
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RCIDL
ADIE
ADIP
Bit 6
ADIF
RX9
TX9
bit 1
TMR0IE
RXDTP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
bit 7/8
TXCKP
Stop
INT0IE
CREN
SYNC
bit
Bit 4
TXIF
TXIE
TXIP
Word 1
RCREG
Start
bit
ADDEN
SENDB
bit 0
BRG16
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 18-8) and asynchronously, if the device is in
Sleep mode (Figure 18-9). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-
high transition is observed on the RX line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
The RCREG (receive buffer) is read after the third word
TMR0IF
CCP1IE
CCP1IP
CCP1IF
bit 7/8
BRGH
FERR
Word 2
RCREG
Bit 2
—
Stop
bit
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
Start
© 2008 Microchip Technology Inc.
WUE
Bit 1
bit
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
RBIF
bit 7/8
Bit 0
Stop
bit
on page
Values
Reset
49
52
52
52
51
51
51
51
51
51