PIC18LF2420-I/SP Microchip Technology, PIC18LF2420-I/SP Datasheet - Page 361

• Manufacturer Part Number: PIC18LF2420-I/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2420-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/USART
• On-chip Adc: 10-chx10-bit
• Number Of Timers: 4
• Core: PIC
• Processor Series: PIC18LF
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 768 B
• Data Rom Size: 256 B
• Mounting Style: Through Hole
• Height: 3.3 mm
• Length: 34.67 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 26-23:
TABLE 26-25: A/D CONVERSION REQUIREMENTS
© 2008 Microchip Technology Inc.
130
131
132
135
TBD
Note 1:
Param
No.
A/D CLK
2:
3:
4:
Note 1:
A/D DATA
SAMPLE
T
T
T
T
T
ADRES
Symbol
BSF ADCON0, GO
AD
CNV
ACQ
SWC
DIS
ADIF
The time of the A/D clock period is dependent on the device frequency and the T
ADRES register may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
On the following cycle of the device clock.
GO
2:
Q4
(1)
If the A/D clock source is selected as RC, a time of T
to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
A/D Clock Period
Conversion Time
(not including acquisition time) (Note 2)
Acquisition Time (Note 3)
Switching Time from Convert → Sample
Discharge Time
132
A/D CONVERSION TIMING
(Note 2)
Characteristic
DD
9
to V
SS
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
8
or V
PIC18F2420/2520/4420/4520
OLD_DATA
SS
7
to V
. . .
SAMPLING STOPPED
DD
CY
). The source impedance (R
CY
is added before the A/D clock starts. This allows the SLEEP instruction
cycle.
. . .
131
130
Min
0.7
1.4
1.4
0.2
—
—
11
—
2
(Note 4)
25.0
25.0
Max
12
—
—
1
3
(1)
(1)
1
Units
T
μs
μs
μs
μs
μs
μs
AD
S
) on the input channels is 50Ω.
0
T
V
T
A/D RC mode
V
-40°C to +85°C
OSC
OSC
DD
DD
AD
= 2.0V;
= 2.0V; A/D RC mode
based, V
based, V
clock divider.
NEW_DATA
DONE
Conditions
DS39631E-page 359
T
CY
REF
REF
≥ 3.0V
full range