ATMEGA649V-8AU Atmel, ATMEGA649V-8AU Datasheet - Page 45
ATMEGA649V-8AU
Manufacturer Part Number
ATMEGA649V-8AU
Description
IC AVR MCU FLASH 64K 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA649V-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
4KB
# I/os (max)
54
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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Price
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10.8
2552K–AVR–04/11
Watchdog Timer
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at V
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in
dog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega329/3290/649/6490 resets and
executes from the Reset Vector. For timing details on the Watchdog Reset, refer to
on page
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in Table 10-1. Refer to
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 47
details.
Table 10-1.
Figure 10-7. Watchdog Timer
WDTON
Unprogrammed
Programmed
46.
Table 10-2 on page
WDT Configuration as a Function of the Fuse Settings of WDTON
Safety
Level
CC
1
2
= 5V. See characterization data for typical values at other V
OSCILLATOR
WATCHDOG
WDT Initial
State
Disabled
Enabled
46. The WDR – Watchdog Reset – instruction resets the Watch-
ATmega329/3290/649/6490
How to Disable the
WDT
Timed sequence
Always enabled
How to Change
Time-out
Timed sequence
Timed sequence
CC
Table 10-2
levels. By
for
45
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