ATMEGA649V-8AU Atmel, ATMEGA649V-8AU Datasheet - Page 70

• Manufacturer Part Number: ATMEGA649V-8AU
• Description: IC AVR MCU FLASH 64K 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA649V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Cpu Family: ATmega
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 54
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

70
ATmega329/3290/649/6490
• SS/PCINT8 – Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an
input regardless of the setting of DDB0. As a Slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit
PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source.
Table 13-7
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 13-7.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Figure 13-5 on page
and
Overriding Signals for Alternate Functions in PB7:PB4
PB7/OC2A/
PCINT15
0
0
0
0
OC2A ENABLE
OC2A
–
PCINT15 •
PCIE1
1
PCINT15 INPUT
–
Table 13-8
relate the alternate functions of Port B to the overriding signals
65. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
PB6/OC1B/
PCINT14
0
0
0
0
OC1B ENABLE
OC1B
–
PCINT14 •
PCIE1
1
PCINT14 INPUT
–
PB5/OC1A/
PCINT13
0
0
0
0
OC1A ENABLE
OC1A
–
PCINT13 •
PCIE1
1
PCINT13 INPUT
–
PB4/OC0A/
PCINT12
0
0
0
0
OC0A ENABLE
OC0A
–
PCINT12 •
PCIE1
1
PCINT12 INPUT
–
2552K–AVR–04/11