DSPIC30F5016-20E/PT Microchip Technology, DSPIC30F5016-20E/PT Datasheet - Page 40
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
DSPIC30F5016-20E/PT
Manufacturer Part Number
DSPIC30F5016-20E/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F5016-30IPT.pdf
(230 pages)
4.DSPIC30F5016-30IPT.pdf
(14 pages)
5.DSPIC30F5016-30IPT.pdf
(6 pages)
6.DSPIC30F5016-30IPT.pdf
(18 pages)
Specifications of DSPIC30F5016-20E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20IP PDF datasheet #2
- DSPIC30F5016-30IPT PDF datasheet #3
- DSPIC30F5016-30IPT PDF datasheet #4
- DSPIC30F5016-30IPT PDF datasheet #5
- DSPIC30F5016-30IPT PDF datasheet #6
- Current page: 40 of 230
- Download datasheet (4Mb)
dsPIC30F5015/5016
4.2.3
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W register.
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to). Address
changes may, therefore, jump beyond boundaries and
still be adjusted correctly.
4.3
Bit-Reversed Addressing is intended to simplify data
reordering for radix-2 FFT algorithms. It is supported by
the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
4.3.1
Bit-Reversed Addressing is enabled when:
1.
2.
3.
FIGURE 4-2:
DS70149D-page 40
Note:
BWM (W register selection) in the MODCON
register is any value other than 15 (the stack can
not be accessed using Bit-Reversed Addressing)
and
the BREN bit is set in the XBREV register and
the addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
b15 b14 b13 b12
b15 b14 b13 b12
Bit-Reversed Addressing
MODULO ADDRESSING
APPLICABILITY
The modulo corrected Effective Address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the Effective Address.
When an address offset (e.g., [W7 + W2])
is used, modulo address correction is per-
formed, but the contents of the register
remains unchanged.
BIT-REVERSED ADDRESSING
IMPLEMENTATION
BIT-REVERSED ADDRESS EXAMPLE
b11 b10 b9 b8
b11 b10 b9 b8
b7 b6 b5 b4
b7 b6 b5 b1
Pivot Point
b3 b2 b1
b2 b3 b4
Sequential Address
Bit-Reversed Address
If the length of a Bit-Reversed buffer is M = 2
then the last ‘N’ bits of the data buffer start address
must be zeros.
XB<14:0> is the Bit-Reversed Address modifier or
‘pivot point’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, Bit-Reversed Addressing will only be
executed for Register Indirect with Pre-Increment or
Post-Increment Addressing and word-sized data writes.
It will not function for any other addressing mode or for
byte-sized data, and normal addresses will be generated
instead. When Bit-Reversed Addressing is active, the W
address pointer will always be added to the address
modifier (XB) and the offset associated with the Register
Indirect Addressing mode will be ignored. In addition, as
word-sized data is a requirement, the LSb of the EA is
ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the Bit-Reversed Pointer.
Note:
Note:
XB = 0x0008 for a 16-word Bit-Reversed Buffer
0
0
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Modulo Addressing and Bit-Reversed
Addressing
together. In the event that the user
attempts to do this, Bit-Reversed Address-
ing will assume priority when active for the
X WAGU, and X WAGU Modulo Address-
ing will be disabled. However, Modulo
Addressing will continue to function in the
X RAGU.
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
© 2008 Microchip Technology Inc.
should
not
be
enabled
N
bytes,
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