PIC18F2685-E/SO Microchip Technology, PIC18F2685-E/SO Datasheet - Page 169

• Manufacturer Part Number: PIC18F2685-E/SO
• Description: IC PIC MCU FLASH 48KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2685-E/SO

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 28
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3328Byte
• Cpu Speed: 40MHz
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

15.3
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP1
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (CCP1M3:CCP1M0). At the same time, the
interrupt flag bit, CCP1IF, is set.
15.3.1
The user must configure the CCP1 (ECCP1) pin as an
output by clearing the appropriate TRIS bit.
FIGURE 15-2:
© 2009 Microchip Technology Inc.
I/O latch)
Note:
Compare Mode
CCP1 PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC2 compare output latch to the default
low level. This is not the PORTC I/O data
latch.
0
1
ECCPR1H
CCPR1H
COMPARE MODE OPERATION BLOCK DIAGRAM
TMR1H
TMR3H
T3CCP1
Comparator
Comparator
ECCPR1L
CCPR1L
TMR1L
TMR3L
Compare
Match
Compare
Match
PIC18F2682/2685/4682/4685
0
1
Set CCP1IF
T3ECCP1
Set CCP1IF
(Timer1/Timer3 Reset, A/D Trigger)
15.3.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP1 module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.3.3
When the Generate Software Interrupt mode is chosen
(CCP1M3:CCP1M0 = 1010), the CCP1 pin is not
affected. Only a CCP1 interrupt is generated, if enabled
and the CCP1IE bit is set.
15.3.4
Both CCP1 modules are equipped with a Special
Event Trigger. This is an internal hardware signal
other modules. The Special Event Trigger is enabled
by selecting the Compare Special Event Trigger mode
(CCP1M3:CCP1M0 = 1011).
For either the CCP1/ECCP1 module, the Special Event
Trigger resets the timer register pair for whichever timer
resource is currently assigned as the module’s time
base. This allows the CCPR1 (ECCPR1) registers to
serve as a programmable period register for either
timer.
generated in Compare mode to trigger actions by
Special Event Trigger
Special Event Trigger
ECCP1CON<3:0>
CCP1CON<3:0>
(Timer1 Reset)
Output
Output
Logic
4
Logic
4
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
S
R
S
R
Q
Q
Output Enable
Output Enable
TRIS
TRIS
DS39761C-page 169
ECCP1 pin
CCP1 pin