PIC18F2685-E/SO Microchip Technology, PIC18F2685-E/SO Datasheet - Page 451

IC PIC MCU FLASH 48KX16 28SOIC

PIC18F2685-E/SO

Manufacturer Part Number
PIC18F2685-E/SO
Description
IC PIC MCU FLASH 48KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F2685-E/SO

Core Size
8-Bit
Program Memory Size
96KB (48K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
28
Eeprom Memory Size
1024Byte
Ram Memory Size
3328Byte
Cpu Speed
40MHz
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
TABLE 27-21: MASTER SSP I
© 2009 Microchip Technology Inc.
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1:
Param.
No.
2:
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
R
HIGH
LOW
F
HD
HD
BUF
B
Maximum pin capacitance = 10 pF for all I
A Fast mode I
parameter 107 ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for
100 kHz mode), before the SCL line is released.
:
:
:
:
:
STA
DAT
STO
STA
DAT
Clock High
Time
Clock Low Time 100 kHz mode
SDA and SCL
Rise Time
SDA and SCL
Fall Time
Start Condition
Setup Time
Start Condition
Hold Time
Data Input
Hold Time
Data Input
Setup Time
Stop Condition
Setup Time
Output Valid
from Clock
Bus Free Time
Bus Capacitive Loading
2
C™ bus device can be used in a Standard mode I
Characteristic
2
C™ BUS DATA REQUIREMENTS
100 kHz mode
400 kHz mode
1 MHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
PIC18F2682/2685/4682/4685
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
2
C pins.
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
2(T
OSC
OSC
OSC
OSC
OSC
OSC
20 + 0.1 C
20 + 0.1 C
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
Min
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
)(BRG + 1)
250
100
4.7
1.3
0
0
B
B
1000
3500
1000
Max
2
300
300
300
300
100
0.9
400
C bus system, but
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
10 to 400 pF
C
10 to 400 pF
Only relevant for
Repeated Start
condition
After this period, the first
clock pulse is generated
(Note 2)
Time the bus must be free
before a new transmission
can start
B
B
is specified to be from
is specified to be from
Conditions
DS39761C-page 451

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