ATXMEGA128D3-AU Atmel, ATXMEGA128D3-AU Datasheet - Page 7

• Manufacturer Part Number: ATXMEGA128D3-AU
• Description: MCU AVR 128K FLASH 3.6V 64TQFP
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA128D3-AU

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: XMEGA
• Core: AVR
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 8 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Operating Supply Voltage: 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. AVR CPU
6.1
6.2
8134I–AVR–12/10
Features
Overview
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The Atmel
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations and control peripherals. Interrupt handling is described in a separate sec-
tion.
Figure 6-1.
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
8/16-bit high performance AVR RISC Architecture
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack Pointer accessible in I/O memory space
Direct addressing of up to 16M bytes of program and data memory
True 16/24-bit access to 16/24-bit I/O registers
Support for 8-, 16- and 32-bit Arithmetic
Configuration Change Protection of system critical features
– 138 instructions
– Hardware multiplier
Figure 6-1 on page 7
®
AVR
Peripheral
Module 1
CPU block diagram
®
XMEGA
CONTROL
STATUS/
Program
Counter
OCD
TM
shows the CPU block diagram.
Peripheral
Module 2
D3 uses the 8/16-bit AVR CPU. The main function of the AVR CPU
Instruction
Instruction
Program
Register
Memory
Decode
Flash
DATA BUS
SRAM
DATA BUS
ALU
EEPROM
32 x 8 General
Registers
Purpose
Multiplier/
DES
PMIC
XMEGA D3
7