AT90CAN64-16MU Atmel, AT90CAN64-16MU Datasheet - Page 136

• Manufacturer Part Number: AT90CAN64-16MU
• Description: IC MCU AVR 64K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 0.5 V to 0.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

136
AT90CAN32/64/128
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
The COMnA1:0, COMnB1:0 and COMnC1:0 control the Output Compare pins (OCnA, OCnB
and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the
OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COMnB1:0 bit are written to one, the OCnB output overrides the normal port func-
tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bit are written to one,
the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-
ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or
OCnC pin must be set in order to enable the output driver.
When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is
dependent of the WGMn3:0 bits setting.
the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 13-1.
Table 13-2
PWM mode.
Table 13-2.
Note:
COMnA1/COMnB1/
COMnA1/COMnB1/
COMnC1
COMnC1
1. A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
0
0
1
1
0
0
1
1
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or
clear is done at TOP.
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast
Compare Output Mode, non-PWM
Compare Output Mode, Fast PWM
COMnA0/COMnB0/
COMnA0/COMnB0/
COMnC0
COMnC0
See “Fast PWM Mode” on page 128.
0
1
0
1
0
1
0
1
Table 13-1
Description
Normal port operation, OCnA/OCnB/OCnC
disconnected.
Toggle OCnA/OCnB/OCnC on Compare Match.
Clear OCnA/OCnB/OCnC on Compare Match (Set
output to low level).
Set OCnA/OCnB/OCnC on Compare Match (Set
output to high level).
Description
Normal port operation, OCnA/OCnB/OCnC
disconnected.
WGMn3=0: Normal port operation,
OCnA/OCnB/OCnC disconnected.
WGMn3=1: Toggle OCnA on Compare Match,
OCnB/OCnC reserved.
Clear OCnA/OCnB/OCnC on Compare Match
Set OCnA/OCnB/OCnC at TOP
Set OCnA/OCnB/OCnC on Compare Match
Clear OCnA/OCnB/OCnC at TOP
(1)
shows the COMnx1:0 bit functionality when
for more details.
7679H–CAN–08/08