AT90CAN64-16MU Atmel, AT90CAN64-16MU Datasheet - Page 253

• Manufacturer Part Number: AT90CAN64-16MU
• Description: IC MCU AVR 64K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 0.5 V to 0.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.10.2
7679H–CAN–08/08
CAN General Status Register - CANGSTA
• Bit 0 – SWRES: Software Reset Request
This auto resettable bit only resets the CAN controller.
• Bit 7 – Reserved Bit
This bit is reserved for future use.
• Bit 6 – OVRG: Overload Frame Flag
This flag does not generate an interrupt.
• Bit 5 – Reserved Bit
This bit is reserved for future use.
• Bit 4 – TXBSY: Transmitter Busy
This flag does not generate an interrupt.
• Bit 3 – RXBSY: Receiver Busy
This flag does not generate an interrupt.
• Bit 2 – ENFG: Enable Flag
Initial Value
Read/Write
Bit
– 0 - standby mode: The on-going transmission (if exists) is normally terminated and the
– 1 - enable mode: The CAN channel enters in enable mode once 11 recessive bits
– 0 - no reset
– 1 - reset: this reset is “ORed” with the hardware reset.
– 0 - no overload frame.
– 1 - overload frame: set by hardware as long as the produced overload frame is sent.
– 0 - transmitter not busy.
– 1 - transmitter busy: set by hardware as long as a frame (data, remote, overload or
– 0 - receiver not busy
– 1 - receiver busy: set by hardware as long as a frame is received or monitored.
CAN channel is frozen (the CONMOB bits of every MOb do not change). The transmitter
constantly provides a recessive level. In this mode, the receiver is not enabled but all the
registers and mailbox remain accessible from CPU.
has been read.
error frame) or an ACK field is sent. Also set when an inter frame space is sent.
Note:
7
-
-
-
A standby mode applied during a reception may corrupt the on-going reception or set the
controller in a wrong state. The controller will restart correctly from this state if a software
reset (SWRES) is applied. If no reset is considered, a possible solution is to wait for a
lake of a receiver busy (RXBSY) before to enter in stand-by mode. The best solution is
first to apply an abort request command (ABRQ) and then wait for the lake of the receiver
busy (RXBSY) before to enter in stand-by mode. In any cases, this standby mode behav-
ior has no effect on the CAN bus integrity.
OVRG
R
6
0
5
-
-
-
TXBSY
4
R
0
RXBSY
R
3
0
ENFG
R
2
0
AT90CAN32/64/128
BOFF
R
1
0
ERRP
R
0
0
CANGSTA
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