AT90CAN64-16MU Atmel, AT90CAN64-16MU Datasheet - Page 308

• Manufacturer Part Number: AT90CAN64-16MU
• Description: IC MCU AVR 64K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN64-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 0.5 V to 0.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.6.5
308
AT90CAN32/64/128
Scanning the Analog Comparator
Figure 23-7. Boundary-scan Cells for Oscillators and Clock Options
Table 23-5
XTAL1/XTAL2 connections as well as external Timer2 clock pin TOSC1 and 32kHz Timer2
Oscillator.
Table 23-5.
Notes:
The relevant Comparator signals regarding Boundary-scan are shown in
Boundary-scan cell from
described in
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Enable Signal
EXTCLKEN
OSCON
OSC32EN
TOSKON
1. Do not enable more than one clock source as clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
3. The main clock configuration is programmed by fuses. As a fuse is not changed run-time, the
From Digital Logic
the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
main clock configuration is considered fixed for a given application. The user is advised to
scan the same clock option as to be used in the final system. The enable signals are sup-
ported in the scan chain because the system logic can disable clock options in sleep modes,
thereby disconnecting the Oscillator pins from the scan path if not provided.
summaries the scan registers for the external clock pin XTAL1, oscillators with
Table
Scan Signals for the Oscillators
Scanned Clock Line
EXTCLK (XTAL1)
OSCCK
OSC32CK
TOSCK
23-6.
Previous
From
Cell
ShiftDR
0
1
ClockDR
Figure 23-9
D
UpdateDR
Q
Next
Cell
To
D
G
is attached to each of these signals. The signals are
Q
Clock Option
External Main Clock
External Crystal
External Ceramic Resonator
Low Freq. External Crystal
32 kHz Timer2 Oscillator
EXTEST
0
1
(1)(2)(3)
XTAL1 / TOSC1
ENABLE
Oscillator
XTAL2 / TOSC2
OUTPUT
Previous
From
Cell
ShiftDR
0
1
ClockDR
Scanned Clock Line
when not Used
D
Figure
FF1
Q
Next
Cell
To
7679H–CAN–08/08
0
1
1
1
23-8. The
To System Logic