ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 156
![MCU AVR 128KB FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128-16MN
Manufacturer Part Number
ATMEGA128-16MN
Description
MCU AVR 128KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8-bit
Timer/Counter
Register
Description
Timer/Counter Control
Register – TCCR2
156
ATmega128
• Bit 7 – FOC2: Force Output Compare
The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written
when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate com-
pare match is forced on the waveform generation unit. The OC2 output is changed according to
its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the
value present in the COM21:0 bits that determines the effect of the forced compare.
A FOC2 strobe will not generate any interrupt, nor will it clear the Timer in CTC mode using
OCR2 as TOP.
The FOC2 bit is always read as zero.
• Bit 6, 3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
page
Table 64. Waveform Generation Mode Bit Description
Note:
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits
are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be
set in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0
bit setting.
normal or CTC mode (non-PWM).
Bit
Read/Write
Initial Value
Mode
0
1
2
3
149.
The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. How-
ever, the functionality and location of these bits are compatible with previous versions of the timer.
WGM21
(CTC2)
Table 65
0
0
1
1
FOC2
W
7
0
WGM20
(PWM2)
shows the COM21:0 bit functionality when the WGM21:0 bits are set to a
WGM20
R/W
0
1
0
1
6
0
COM21
Timer/Counter Mode
of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
R/W
5
0
COM20
R/W
0
4
WGM21
R/W
3
0
TOP
0xFF
0xFF
OCR2
0xFF
CS22
R/W
2
0
Table 64
Update of
OCR2 at
Immediate
TOP
Immediate
BOTTOM
CS21
R/W
1
0
and
“Modes of Operation” on
CS20
R/W
0
0
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX
TCCR2
2467V–AVR–02/11
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