ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 77
![MCU AVR 128KB FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128-16MN
Manufacturer Part Number
ATMEGA128-16MN
Description
MCU AVR 128KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Alternate Functions of
Port D
2467V–AVR–02/11
Table 35. Overriding Signals for Alternate Functions in PC3..PC0
Note:
The Port D pins with alternate functions are shown in
Table 36. Port D Pins Alternate Functions
Note:
The alternate pin configuration is as follows:
• T2 – Port D, Bit 7
T2, Timer/Counter2 counter source.
• T1 – Port D, Bit 6
T1, Timer/Counter1 counter source.
• XCK1 – Port D, Bit 5
XCK1, USART1 External clock. The Data Direction Register (DDD4) controls whether the clock
is output (DDD4 set) or input (DDD4 cleared). The XCK1 pin is active only when the USART1
operates in Synchronous mode.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Port Pin
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
1. XMM = 0 in ATmega103 compatibility mode.
1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode.
PC3/A11
SRE • (XMM<5)
0
SRE • (XMM<5)
1
SRE • (XMM<5)
A11
0
0
–
–
Alternate Function
T2 (Timer/Counter2 Clock Input)
T1 (Timer/Counter1 Clock Input)
XCK1
ICP1 (Timer/Counter1 Input Capture Pin)
INT3/TXD1
INT2/RXD1
INT1/SDA
INT0/SCL
(1)
(USART1 External Clock Input/Output)
(1)
(1)
(1)
(1)
(External Interrupt0 Input or TWI Serial CLock)
(External Interrupt1 Input or TWI Serial DAta)
(External Interrupt3 Input or UART1 Transmit Pin)
(External Interrupt2 Input or UART1 Receive Pin)
PC2/A10
0
1
A10
0
0
–
–
SRE • (XMM<6)
SRE • (XMM<6)
SRE • (XMM<6)
PC1/A9
SRE • (XMM<7)
0
SRE • (XMM<7)
1
SRE • (XMM<7)
A9
0
0
–
–
Table
36.
(1)
PC0/A8
SRE • (XMM<7)
0
SRE • (XMM<7)
1
SRE • (XMM<7)
A8
0
0
–
–
ATmega128
77
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