PIC18F2685-I/SO Microchip Technology, PIC18F2685-I/SO Datasheet - Page 165

IC PIC MCU FLASH 48KX16 28SOIC

PIC18F2685-I/SO

Manufacturer Part Number
PIC18F2685-I/SO
Description
IC PIC MCU FLASH 48KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F2685-I/SO

Program Memory Type
FLASH
Program Memory Size
96KB (48K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
15.0
PIC18F2682/2685 devices have one CCP1 module.
PIC18F4682/4685 devices have two CCP1 (Capture/
Compare/PWM) modules. CCP1, discussed in this
chapter, implements standard Capture, Compare and
Pulse-Width Modulation (PWM) modes.
ECCP1 implements an Enhanced PWM mode. The
ECCP1 implementation is discussed in Section 16.0
“Enhanced
Module”.
REGISTER 15-1:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3-0
Note 1:
U-0
CAPTURE/COMPARE/PWM
(CCP1) MODULES
Selected by CANCAP (CIOCON<4>) bit; overrides the CCP1 input pin source.
Capture/Compare/PWM
Unimplemented: Read as ‘0’
DC1B1:DC1B0: CCP1 Module PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DC1B9:DC1B2) of the duty cycle are found in CCPR1L.
CCP1M3:CCP1M0: CCP1 Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP1 module)
0001 = Reserved
0010 = Compare mode; toggle output on match (CCP1IF bit is set)
0011 = Reserved
0100 = Capture mode; every falling edge or CAN message received (time-stamp)
0101 = Capture mode; every rising edge or CAN message received (time-stamp)
0110 = Capture mode; every 4th rising edge or every 4th CAN message received (time-stamp)
0111 = Capture mode; every 16th rising edge or every 16th CAN message received (time-stamp)
1000 = Compare mode; initialize CCP1 pin low; on compare match, force CCP1 pin high
1001 = Compare mode; initialize CCP pin high; on compare match, force CCP1 pin low
1010 = Compare mode; generate software interrupt on compare match (CCP1IF bit is set,
1011 = Compare mode; trigger special event; reset timer (TMR1 or TMR3, CCP1IF bit is set)
11xx = PWM mode
U-0
CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER
(CCPIF bit is set)
(CCPIF bit is set)
CCP1 pin reflects I/O state)
W = Writable bit
‘1’ = Bit is set
DC1B1
R/W-0
PIC18F2682/2685/4682/4685
(ECCP1)
DC1B0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCP1M3
R/W-0
The CCP1 module contains a 16-bit register which can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP1 module operation in the
following sections is described with respect to CCP1,
but is equally applicable to ECCP1.
Capture/ and Compare operations described in this
chapter apply to all standard and Enhanced CCP1
modules. The operations of PWM mode, described in
Section 15.4 “PWM Mode”, apply to CCP1 only.
CCP1M2
R/W-0
x = Bit is unknown
CCP1M1
R/W-0
(1)
(1)
DS39761C-page 165
CCP1M0
R/W-0
(1)
bit 0
(1)

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