PIC18F2685-I/SO Microchip Technology, PIC18F2685-I/SO Datasheet - Page 478

• Manufacturer Part Number: PIC18F2685-I/SO
• Description: IC PIC MCU FLASH 48KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2685-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2682/2685/4682/4685
T
T0CON Register
Table Reads/Table Writes .................................................. 66
TBLRD ............................................................................. 403
TBLWT ............................................................................. 404
Time-out in Various Situations (table) ................................ 47
Timer0 .............................................................................. 149
Timer1 .............................................................................. 153
Timer2 .............................................................................. 159
Timer3 .............................................................................. 161
Timing Diagrams
DS39761C-page 478
PSA Bit ..................................................................... 151
T0CS Bit ................................................................... 150
T0PS2:T0PS0 Bits ................................................... 151
T0SE Bit ................................................................... 150
Associated Registers ............................................... 151
Clock Source Edge Select (T0SE Bit) ...................... 150
Clock Source Select (T0CS Bit) ............................... 150
Operation ................................................................. 150
Overflow Interrupt .................................................... 151
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 150
16-Bit Read/Write Mode ........................................... 155
Associated Registers ............................................... 157
Interrupt .................................................................... 156
Operation ................................................................. 154
Oscillator .................................................................. 155
Resetting, Using a Special Event Trigger
Special Event Trigger (ECCP1) ............................... 176
Use as a Real-Time Clock ....................................... 156
Associated Registers ............................................... 160
Interrupt .................................................................... 160
Operation ................................................................. 159
Output ...................................................................... 160
PR2 Register .................................................... 171, 177
TMR2 to PR2 Match Interrupt .................................. 171
16-Bit Read/Write Mode ........................................... 163
Associated Registers ............................................... 163
Operation ................................................................. 162
Oscillator .................................................. 153, 161, 163
Overflow Interrupt .................................................... 163
Special Event Trigger (ECCP1) ............................... 163
TMR3H Register .............................................. 153, 161
TMR3L Register ............................................... 153, 161
A/D Conversion ........................................................ 454
Acknowledge Sequence .......................................... 222
Asynchronous Reception ......................................... 241
Asynchronous Transmission .................................... 239
Asynchronous Transmission (Back-to-Back) ........... 239
Automatic Baud Rate Calculation ............................ 237
Auto-Wake-up Bit (WUE) During Normal Operation 242
Auto-Wake-up Bit (WUE) During Sleep ................... 242
Baud Rate Generator with Clock Arbitration ............ 216
BRG Overflow Sequence ......................................... 237
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 440
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Layout Considerations ..................................... 156
Output (CCP1) ................................................. 156
During Start Condition ...................................... 225
(Case 1) ........................................................... 226
(Case 2) ........................................................... 226
Bus Collision During a Start Condition
Bus Collision During a Start Condition
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision for Transmit and
Capture/Compare/PWM (All CCP Modules) ............ 442
CLKO and I/O .......................................................... 439
Clock Synchronization ............................................. 209
Clock/Instruction Cycle .............................................. 67
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 444
Example SPI Master Mode (CKE = 1) ..................... 445
Example SPI Slave Mode (CKE = 0) ....................... 446
Example SPI Slave Mode (CKE = 1) ....................... 447
External Clock (All Modes Except PLL) ................... 437
Fail-Safe Clock Monitor ........................................... 359
First Start Bit Timing ................................................ 217
Full-Bridge PWM Output .......................................... 181
Half-Bridge PWM Output ......................................... 180
High/Low-Voltage Detect Characteristics ................ 434
High-Voltage Detect (VDIRMAG = 1) ...................... 272
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect (VDIRMAG = 0) ....................... 271
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4682/4685) ................... 443
Parallel Slave Port (PSP) Read ............................... 147
Parallel Slave Port (PSP) Write ............................... 147
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 183
PWM Direction Change at Near 100% Duty Cycle .. 183
PWM Output ............................................................ 171
Repeated Start Condition ........................................ 218
Reset, Watchdog Timer (WDT), Oscillator
Send Break Character Sequence ............................ 243
Slave Synchronization ............................................. 195
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 194
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 448
C Bus Start/Stop Bits ............................................ 448
C Master Mode (7 or 10-Bit Transmission) ........... 220
C Master Mode (7-Bit Reception) .......................... 221
C Slave Mode (10-Bit Reception, SEN = 0) .......... 206
C Slave Mode (10-Bit Reception, SEN = 1) .......... 211
C Slave Mode (10-Bit Transmission) .................... 207
C Slave Mode (7-Bit Reception, SEN = 0) ............ 204
C Slave Mode (7-Bit Reception, SEN = 1) ............ 210
C Slave Mode (7-Bit Transmission) ...................... 205
C Slave Mode General Call Address Sequence (7 or
(SCL = 0) ......................................................... 225
(SDA Only) ...................................................... 224
(Case 1) ........................................................... 227
(Case 2) ........................................................... 227
Acknowledge ................................................... 223
(Master/Slave) ................................................. 452
(Master/Slave) ................................................. 452
10-Bit Address Mode) ...................................... 212
Auto-Restart Disabled) .................................... 186
Auto-Restart Enabled) ..................................... 186
Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 440
V
DD
Rise > T
2
2
C Bus Data ........................................ 450
C Bus Start/Stop Bits ........................ 450
PWRT
© 2009 Microchip Technology Inc.
) ............................................ 49
DD
,