PIC18F2685-I/SO Microchip Technology, PIC18F2685-I/SO Datasheet - Page 341

• Manufacturer Part Number: PIC18F2685-I/SO
• Description: IC PIC MCU FLASH 48KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2685-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

23.14 Error Detection
The CAN protocol provides sophisticated error
detection mechanisms. The following errors can be
detected.
23.14.1
With the Cyclic Redundancy Check (CRC), the trans-
mitter calculates special check bits for the bit
sequence, from the start of a frame until the end of the
data field. This CRC sequence is transmitted in the
CRC field. The receiving node also calculates the CRC
sequence using the same formula and performs a
comparison to the received sequence. If a mismatch is
detected, a CRC error has occurred and an error frame
is generated. The message is repeated.
23.14.2
In the Acknowledge field of a message, the transmitter
checks if the Acknowledge slot (which was sent out as
a recessive bit) contains a dominant bit. If not, no other
node has received the frame correctly. An Acknowl-
edge error has occurred, an error frame is generated
and the message will have to be repeated.
23.14.3
If a node detects a dominant bit in one of the four
segments, including End-of-Frame, interframe space,
Acknowledge delimiter or CRC delimiter, then a form
error has occurred and an error frame is generated.
The message is repeated.
23.14.4
A bit error occurs if a transmitter sends a dominant bit
and detects a recessive bit, or if it sends a recessive bit
and detects a dominant bit, when monitoring the actual
bus level and comparing it to the just transmitted bit. In
the case where the transmitter sends a recessive bit
and a dominant bit is detected during the arbitration
field and the Acknowledge slot, no bit error is
generated because normal arbitration is occurring.
23.14.5
lf, between the Start-of-Frame and the CRC delimiter,
six consecutive bits with the same polarity are
detected, the bit stuffing rule has been violated. A stuff
bit error occurs and an error frame is generated. The
message is repeated.
© 2009 Microchip Technology Inc.
CRC ERROR
ACKNOWLEDGE ERROR
FORM ERROR
BIT ERROR
STUFF BIT ERROR
PIC18F2682/2685/4682/4685
23.14.6
Detected errors are made public to all other nodes via
error frames. The transmission of the erroneous
message is aborted and the frame is repeated as soon
as possible. Furthermore, each CAN node is in one of
the three error states: “error-active”, “error-passive” or
“bus-off”, according to the value of the internal error
counters. The error-active state is the usual state
where the bus node can transmit messages and
activate error frames (made of dominant bits) without
any restrictions. In the error-passive state, messages
and passive error frames (made of recessive bits) may
be transmitted. The bus-off state makes it temporarily
impossible for the station to participate in the bus
communication. During this state, messages can
neither be received nor transmitted.
23.14.7
The PIC18F2682/2685/4682/4685 devices contain two
error counters: the Receive Error Counter (RXERRCNT)
and the Transmit Error Counter (TXERRCNT). The
values of both counters can be read by the MCU. These
counters
accordance with the CAN bus specification.
The PIC18F2682/2685/4682/4685 devices are error-
active if both error counters are below the error-passive
limit of 128. They are error-passive if at least one of the
error counters equals or exceeds 128. They go to bus-
off if the transmit error counter equals or exceeds the
bus-off limit of 256. The devices remain in this state
until the bus-off recovery sequence is received. The
bus-off recovery sequence consists of 128 occurrences
of 11 consecutive recessive bits (see Figure 23-8).
Note that the CAN module, after going bus-off, will
recover back to error-active without any intervention by
the MCU if the bus remains Idle for 128 x 11 bit times.
If this is not desired, the error Interrupt Service Routine
should address this. The current Error mode of the
CAN module can be read by the MCU via the
COMSTAT register.
Additionally, there is an Error State Warning flag bit,
EWARN, which is set if at least one of the error
counters equals or exceeds the error warning limit of
96. EWARN is reset if both error counters are less than
the error warning limit.
are
ERROR STATES
ERROR MODES AND ERROR
COUNTERS
incremented
or
DS39761C-page 341
decremented
in