AT90CAN128-16MU Atmel, AT90CAN128-16MU Datasheet - Page 282
![IC MCU AVR 128K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MU
Manufacturer Part Number
AT90CAN128-16MU
Description
IC MCU AVR 128K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
AT90CANx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, JTAG, PS2, SPI, SRAM, USB
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
3
Operating Supply Voltage
1.8 V, 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64QFN EP
Device Core
AVR
Family Name
90C
Maximum Speed
16 MHz
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90CAN128-16MU
Manufacturer:
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Quantity:
12 000
Company:
Part Number:
AT90CAN128-16MU
Manufacturer:
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Quantity:
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Part Number:
AT90CAN128-16MU
Manufacturer:
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21.6.3
21.6.4
282
AT90CAN32/64/128
Offset Compensation Schemes
ADC Accuracy Definitions
Figure 21-9. ADC Power Connections
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea-
surements as much as possible. The remaining offset in the analog path can be measured
directly by selecting the same channel for both differential inputs. This offset residue can be then
subtracted in software from the measurement results. Using this kind of software based offset
correction, offset on any channel can be reduced below one LSB.
An n-bit single-ended ADC converts a voltage linearly between GND and V
(LSBs). The lowest code is read as 0, and the highest code is read as 2
Several parameters describe the deviation from the ideal behavior:
1. Keep analog signal paths as short as possible. Make sure analog tracks run over the
2. The AV
3. Use the ADC noise canceler function to reduce induced noise from the CPU.
4. If any ADC port pins are used as digital outputs, it is essential that these do not switch
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
(at 0.5 LSB). Ideal value: 0 LSB.
analog ground plane, and keep them well away from high-speed switching digital
tracks.
an LC network as shown in
while a conversion is in progress.
CC
pin on the device should be connected to the digital V
Analog Ground Plane
Figure
100nF
21-9.
(ADC7) PF7
(ADC6) PF6
(ADC5) PF5
(ADC4) PF4
(ADC3) PF3
(ADC2) PF2
(ADC1) PF1
(ADC0) PF0
(AD0) PA0
AREF
AVCC
GND
GND
VCC
51
52
53
54
55
56
57
58
59
60
61
61
62
62
63
63
64
64
1
CC
n
supply voltage via
-1.
REF
7679H–CAN–08/08
in 2
n
steps
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