AT90CAN128-16MU Atmel, AT90CAN128-16MU Datasheet - Page 349
![IC MCU AVR 128K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MU
Manufacturer Part Number
AT90CAN128-16MU
Description
IC MCU AVR 128K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
AT90CANx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, JTAG, PS2, SPI, SRAM, USB
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
3
Operating Supply Voltage
1.8 V, 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64QFN EP
Device Core
AVR
Family Name
90C
Maximum Speed
16 MHz
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90CAN128-16MU
Manufacturer:
IR
Quantity:
12 000
Company:
Part Number:
AT90CAN128-16MU
Manufacturer:
ATMEL
Quantity:
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Part Number:
AT90CAN128-16MU
Manufacturer:
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25.7.2
25.7.3
25.8
7679H–CAN–08/08
SPI Serial Programming
Pin Mapping
Parameters
Figure 25-7. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
Table 25-13. Pin Mapping Serial Programming
The Flash parameters are given in
Table 25-12 on page
When writing serial data to the AT90CAN32/64/128, data is clocked on the rising edge of SCK.
When reading data from the AT90CAN32/64/128, data is clocked on the falling edge of SCK.
To program and verify the AT90CAN32/64/128 in the serial programming mode, the following
sequence is recommended (See four byte instruction formats in
MISO (PDO)
MOSI (PDI)
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
Symbol
SCK
XTAL1 pin.
341.
Pins
PE0
PE1
PB1
ck
ck
PDO
SCK
PDI
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
Table 25-11 on page 341
PE0
PE1
PB1
XTAL1
RESET
GND
(1)
I/O
O
I
I
AVCC
AT90CAN32/64/128
VCC
and the EEPROM parameters in
Table
+2.7 - +5.5V
+2.7 - +5.5V
ck
ck
Serial Data out
Description
Serial Data in
25-15):
Serial Clock
≥ 12 MHz
≥ 12 MHz
349
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