AT91SAM7X512-AU Atmel, AT91SAM7X512-AU Datasheet - Page 209
AT91SAM7X512-AU
Manufacturer Part Number
AT91SAM7X512-AU
Description
MCU ARM 512K HS FLASH 100-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X512-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
128 KB
Interface Type
CAN, SPI, SSC, TWI, USART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
13
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
No. Of I/o's
62
Ram Memory Size
128KB
Cpu Speed
55MHz
No. Of Timers
3
No. Of Pwm Channels
4
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7X512-AU
Manufacturer:
Atmel
Quantity:
10 000
Company:
Part Number:
AT91SAM7X512-AU
Manufacturer:
ATMEL
Quantity:
717
- Current page: 209 of 687
- Download datasheet (11Mb)
26.4.2.3
26.4.2.4
26.4.2.5
6120H–ATARM–17-Feb-09
Receiver Ready
Receiver Overrun
Parity Error
Figure 26-4. Start Bit Detection
Figure 26-5. Character Reception
When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY sta-
tus bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the
receive holding register DBGU_RHR is read.
Figure 26-6. Receiver Ready
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the
last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in
DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with
the bit RSTSTA (Reset Status) at 1.
Figure 26-7. Receiver Overrun
Each time a character is received, the receiver calculates the parity of the received data bits, in
accordance with the field PAR in DBGU_MR. It then compares the result with the received parity
Example: 8-bit, parity enabled 1 stop
Sampling
RXRDY
Sampling Clock
RXRDY
OVRE
DRXD
DRXD
DRXD
Baud Rate
DRXD
Clock
S
S
0.5 bit
period
D0
D0
True Start Detection
D1
D1
period
D2
1 bit
D2
AT91SAM7X512/256/128 Preliminary
D3
D0
D3
D4
D4
D1
D5
D5
D6
D6
True Start
Detection
D2
D7
D7
P
P
D3
stop
S
S
D4
Read DBGU_RHR
D0
D0
D1
D1
D5
D2
D2
D3
D3
D6
D4
D4
D5
D5
D7
D6
D6
Parity Bit
D7
D7
P
P
stop
Stop Bit
D0
RSTSTA
209
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