LPC1111FHN33/101,5 NXP Semiconductors, LPC1111FHN33/101,5 Datasheet - Page 5
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LPC1111FHN33/101,5
Manufacturer Part Number
LPC1111FHN33/101,5
Description
IC MCU 32BIT 8KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC1100r
Datasheets
1.LPC1114FHN333015.pdf
(2 pages)
2.LPC1114FHN333015.pdf
(66 pages)
3.LPC1114FHN333015.pdf
(66 pages)
Specifications of LPC1111FHN33/101,5
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC11
Core
ARM Cortex M0
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Number Of Programmable I/os
28
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M0
Family Name
LPC1100
Maximum Speed
50 MHz
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4957
935290771551
935290771551
NXP Semiconductors
5. Block diagram
LPC1111_12_13_14
Product data sheet
Fig 1.
DTR, DSR
DCD
CT32B0_MAT[3:0]
CT32B1_MAT[3:0]
CT16B0_MAT[2:0]
CT16B1_MAT[1:0]
GPIO ports
(1) LQFP48 and PLCC44 packages only.
PIO0/1/2/3
CT32B0_CAP0
CT32B1_CAP0
CT16B0_CAP0
CT16B1_CAP0
(1)
, RI
LPC1111/12/13/14 block diagram
(1)
(1)
, CTS,
, RTS
RXD
TXD
LPC1111/12/13/14
HIGH-SPEED
GPIO
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
system bus
UART
slave
CORTEX-M0
TEST/DEBUG
INTERFACE
SWD
All information provided in this document is subject to legal disclaimers.
ARM
Rev. 4 — 10 February 2011
8/16/24/32 kB
slave
FLASH
AHB-LITE BUS
slave
AHB TO APB
BRIDGE
slave
2/4/8 kB
SRAM
POR
IRC
32-bit ARM Cortex-M0 microcontroller
slave
XTALOUT
LPC1111/12/13/14
SYSTEM CONTROL
POWER CONTROL,
ROM
IOCONFIG
GENERATION,
10-bit ADC
FUNCTIONS
I
2
SPI1
SYSTEM
C-BUS
WDT
SPI0
PMU
XTALIN
CLOCK
clocks and
controls
(1)
RESET
002aae696
© NXP B.V. 2011. All rights reserved.
CLKOUT
AD[7:0]
SCL
SDA
SCK0, SSEL0
MISO0, MOSI0
SCK1, SSEL1
MISO1, MOSI1
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