LPC2194HBD64/01,15 NXP Semiconductors, LPC2194HBD64/01,15 Datasheet - Page 7

IC ARM7 MCU FLASH 256K 64-LQFP

LPC2194HBD64/01,15

Manufacturer Part Number
LPC2194HBD64/01,15
Description
IC ARM7 MCU FLASH 256K 64-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2100r
Datasheet

Specifications of LPC2194HBD64/01,15

Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
64-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
60MHz
Connectivity
CAN, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
46
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
LPC21
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SPI/UART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
46
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4310 - EVAL BOARD LPC2158 W/LCD568-4297 - BOARD EVAL LPC21XX MCB2100622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4316
935284881151
LPC2194HBD64/01-S
LPC2194HBD64/01-S

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Quantity
Price
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NXP Semiconductors
Table 2.
LPC2194_5
Product data sheet
Symbol
P0[30]/AIN3/
EINT3/CAP0[0]
P1[0] to P1[31]
P1[16]/
TRACEPKT0
P1[17]/
TRACEPKT1
P1[18]/
TRACEPKT2
P1[19]/
TRACEPKT3
P1[20]/
TRACESYNC
P1[21]/
PIPESTAT0
P1[22]/
PIPESTAT1
P1[23]/
PIPESTAT2
P1[24]/
TRACECLK
P1[25]/EXTIN0
P1[26]/RTCK
P1[27]/TDO
P1[28]/TDI
P1[29]/TCK
P1[30]/TMS
P1[31]/TRST
TD1
RESET
XTAL1
XTAL2
V
SS
Pin description
Pin
15
16
12
8
4
48
44
40
36
32
28
24
64
60
56
52
20
10
57
62
61
6, 18, 25,
42, 50
…continued
Type Description
I
I
I
I/O
O
O
O
O
O
O
O
O
O
I
I/O
O
I
I
I
I
O
I
I
O
I
AIN3 — A/D converter, input 3. This analog input is always connected to its pin.
EINT3 — External interrupt 3 input.
CAP0[0] — Capture input for Timer 0, channel 0.
Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit.
The operation of port 1 pins depends upon the pin function selected via the Pin
Connect Block. Pins 0 through 15 of port 1 are not available.
Trace Packet, bit 0. Standard I/O port with internal pull-up.
Trace Packet, bit 1. Standard I/O port with internal pull-up.
Trace Packet, bit 2. Standard I/O port with internal pull-up.
Trace Packet, bit 3. Standard I/O port with internal pull-up.
Trace Synchronization. Standard I/O port with internal pull-up.
Note: LOW on this pin while RESET is LOW, enables pins P1[25:16] to operate as
Trace port after reset.
Pipeline Status, bit 0. Standard I/O port with internal pull-up.
Pipeline Status, bit 1. Standard I/O port with internal pull-up.
Pipeline Status, bit 2. Standard I/O port with internal pull-up.
Trace Clock. Standard I/O port with internal pull-up.
External Trigger Input. Standard I/O with internal pull-up.
Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger
synchronization when processor frequency varies. Bidirectional pin with internal
pull-up.
Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to operate as
Debug port after reset.
Test Data out for JTAG interface.
Test Data in for JTAG interface.
Test Clock for JTAG interface. This clock must be slower than
(CCLK) for the JTAG interface to operate.
Test Mode Select for JTAG interface.
Test Reset for JTAG interface.
CAN1 transmitter output.
external reset input; a LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
input to the oscillator circuit and internal clock generator circuits.
output from the oscillator amplifier.
ground: 0 V reference.
Rev. 05 — 10 December 2007
Single-chip 16/32-bit microcontroller
1
LPC2194
6
© NXP B.V. 2007. All rights reserved.
of the CPU clock
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