LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 403

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
Table 365. OTG Status Control register (OTGStCtrl - address 0xFFE0 C110) bit description
Bit
1:0
3:2
4
5
6
7
8
9
10
15:11 -
31:16 TMR_CNT
2. Free running mode: an interrupt is generated at the end of TIMEOUT_CNT (see
Section 15–7.7 “OTG Timer Register (OTGTmr - 0xFFE0
and the timer value is reloaded into the counter. The timer is not disabled in this
mode.
Symbol
PORT_FUNC
TMR_SCALE
TMR_MODE
TMR_EN
TMR_RST
-
B_HNP_TRACK
A_HNP_TRACK
PU_REMOVED
Rev. 04 — 26 August 2009
Description
Controls the function of ports U1 and U2. Bit 0 is set or
cleared by hardware when B_HNP_TRACK or
A_HNP_TRACK is set and HNP succeeds. See
Section
Timer scale selection. This field determines the duration
of each timer count.
00: 10 μ s (100 KHz)
01: 100 μ s (10 KHz)
10: 1000 μ s (1 KHz)
11: Reserved
Timer mode selection.
0: monoshot
1: free running
Timer enable. When set, TMR_CNT increments. When
cleared, TMR_CNT is reset to 0.
Timer reset. Writing one to this bit resets TMR_CNT to 0.
This provides a single bit control for the software to
restart the timer when the timer is enabled.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Enable HNP tracking for B-device (peripheral), see
Section
HNP_SUCCESS or HNP_FAILURE is set.
Enable HNP tracking for A-device (host), see
Section
HNP_SUCCESS or HNP_FAILURE is set.
When the B-device changes its role from peripheral to
host, software sets this bit when it removes the D+
pull-up, see
HNP_SUCCESS or HNP_FAILURE is set.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Current timer count value.
15–8.
15–8. Hardware clears this bit when
15–8. Hardware clears this bit when
Section
Chapter 15: LPC24XX USB OTG controller
15–8. Hardware clears this bit when
C114)”), the TMR bit is set,
UM10237
© NXP B.V. 2009. All rights reserved.
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0x0
Reset
Value
-
0x0
0
0
0
NA
0
0
0
NA