LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 476
LPC2468FET208,551
Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S
935283234551
LPC2468FET208-S
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LPC2468FET208,551
Manufacturer:
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Quantity:
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Table 420. Mode register (CAN1MOD - address 0xE004 4000, CAN2MOD - address 0xE004 8000) bit description
[1]
[2]
[3]
[4]
[5]
[6]
UM10237_4
User manual
Bit Symbol Value
2
3
4
5
6
7
During a Hardware reset or when the Bus Status bit is set '1' (Bus-Off), the Reset Mode bit is set '1' (present). After the Reset Mode bit
is set '0' the CAN Controller will wait for:
- one occurrence of Bus-Free signal (11 recessive bits), if the preceding reset has been caused by a Hardware reset or a CPU-initiated
reset.
- 128 occurrences of Bus-Free, if the preceding reset has been caused by a CAN Controller initiated Bus-Off, before re-entering the
Bus-On mode.
This mode of operation forces the CAN Controller to be error passive. Message Transmission is not possible. The Listen Only Mode can
be used e.g. for software driven bit rate detection and "hot plugging".
A write access to the bits MOD.1 and MOD.2 is possible only if the Reset Mode is entered previously.
Transmit Priority Mode is explained in more detail in
The CAN Controller will enter Sleep Mode, if the Sleep Mode bit is set '1' (sleep), there is no bus activity, and none of the CAN interrupts
is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. The CAN
Controller will wake up if SM is set LOW (wake-up) or there is bus activity. On wake-up, a Wake-up Interrupt is generated. A sleeping
CAN Controller which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits
(Bus-Free sequence). Note that setting of SM is not possible in Reset Mode. After clearing of Reset Mode, setting of SM is possible only
when Bus-Free is detected again.
The LOM and STM bits can only be written if the RM bit is 1 prior to the write operation.
STM
TPM
SM
RPM
-
TM
[5]
[3][6]
[4]
0(normal)
1(self test)
0(CAN ID)
1(local prio)
0(wake-up)
1(sleep)
0(low active)
1(high active) RD input is active High (dominant bit = 1) -- reverse polarity.
-
0(disabled)
1(enabled)
8.2 Command Register (CAN1CMR - 0xE004 x004, CAN2CMR -
0xE004 8004)
Writing to this write-only register initiates an action within the transfer layer of the CAN
Controller. Bits not listed should be written as 0. Reading this register yields zeroes.
At least one internal clock cycle is needed for processing between two commands.
Function
Self Test Mode.
A transmitted message must be acknowledged to be considered successful.
The controller will consider a Tx message successful even if there is no
acknowledgment received.
In this mode a full node test is possible without any other active node on the bus
using the SRR bit in CANxCMR.
Transmit Priority Mode.
The transmit priority for 3 Transmit Buffers depends on the CAN Identifier.
The transmit priority for 3 Transmit Buffers depends on the contents of the Tx
Priority register within the Transmit Buffer.
Sleep Mode.
Normal operation.
The CAN controller enters Sleep Mode if no CAN interrupt is pending and there
is no bus activity. See the Sleep Mode description
Receive Polarity Mode.
RD input is active Low (dominant bit = 0).
Reserved, user software should not write ones to reserved bits.
Test Mode.
Normal operation.
The TD pin will reflect the bit, detected on RD pin, with the next positive edge of
the system clock.
Rev. 04 — 26 August 2009
Section 18–6.3 “Transmit Buffers
Chapter 18: LPC24XX CAN controllers CAN1/2
(TXB)”.
Section 18–9.2 on page
UM10237
© NXP B.V. 2009. All rights reserved.
494.
Reset
Value
0
0
0
0
0
0
476 of 792
RM
Set
x
x
0
x
0
x
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