ST7FOXK1T6TR STMicroelectronics, ST7FOXK1T6TR Datasheet - Page 114

IC MCU 8BIT 4K FLASH 20LQFP

ST7FOXK1T6TR

Manufacturer Part Number
ST7FOXK1T6TR
Description
IC MCU 8BIT 4K FLASH 20LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FOXK1T6TR

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST7FOXx
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 1 Channel
For Use With
497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FOXK1T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
On-chip peripherals
10.3.5
10.3.6
114/226
Interrupts
Table 40.
The TBxF and ICF interrupt events are connected to separate interrupt vectors (see
Section 7:
They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the
interrupt mask in the CC register is reset (RIM instruction).
Register description
Lite Timer Control/Status register 2 (LTCSR2)
Reset value: 0000 0000 (00h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = TB2IE Timebase 2 Interrupt enable bit
Bit 0 = TB2F Timebase 2 Interrupt flag
Timebase 1 Event
Timebase 2 Event
Interrupt Event
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
7
0
IC Event
Interrupts).
Description of interrupt events
0
Event
TB1F
TB2F
Flag
ICF
0
Control
Enable
Read / Write
0
TB1IE
TB2IE
ICIE
Bit
0
ST7FOXF1, ST7FOXK1, ST7FOXK2
from
Wait
Exit
Yes
0
Active
from
Exit
Halt
Yes
No
No
TB2IE
from
Exit
Halt
TB2F
No
0

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