ST7FOXK1T6TR STMicroelectronics, ST7FOXK1T6TR Datasheet - Page 135

• Manufacturer Part Number: ST7FOXK1T6TR
• Description: IC MCU 8BIT 4K FLASH 20LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST7FOXF1, ST7FOXK1, ST7FOXK2
Note:
Note:
If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input edge 2
Bit 0 = EXEDG External clock edge
Timer A Control/status register (TACSR)
Reset value: 0000 0000 (00h)
The 3 least significant bits are not used.
Bit 7 = ICF1 Input capture flag 1
Bit 6 = OCF1 Output compare flag 1
Bit 5 = TOF Timer overflow flag
Reading or writing the ACLR register does not clear TOF.
ICF1
10: Timer clock = f
11: Timer clock = external clock (where available)
This bit determines which type of level transition on the ICAP2 pin triggers the capture.
0: A falling edge triggers the capture
1: A rising edge triggers the capture
This bit determines which type of level transition on the external clock pin EXTCLK
triggers the counter register.
0: A falling edge triggers the counter register
1: A rising edge triggers the counter register
0: No input capture (reset value)
1: An input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.
0: No match (reset value)
1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC1R (OC1LR) register.
0: No timer overflow (reset value)
1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first
read the SR register, then read or write the low byte of the CR (CLR) register.
7
OCF1
CPU
TOF
/8
ICF2
Read Only
OCF2
TIMD
On-chip peripherals
Reserved
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